1. 15 5月, 2020 1 次提交
    • S
      drm/i915: Add TGL+ SAGV support · 7241c57d
      Stanislav Lisovskiy 提交于
      Starting from TGL we need to have a separate wm0
      values for SAGV and non-SAGV which affects
      how calculations are done.
      
      v2: Remove long lines
      v3: Removed COLOR_PLANE enum references
      v4, v5, v6: Fixed rebase conflict
      v7: - Removed skl_plane_wm_level accessor from skl_allocate_pipe_ddb(Ville)
          - Removed sagv_uv_wm0(Ville)
          - can_sagv->use_sagv_wm(Ville)
      
      v8: - Moved tgl_crtc_can_enable_sagv function up(Ville)
          - Changed comment regarding pipe_wm usage(Ville)
          - Call intel_can_enable_sagv and tgl_compute_sagv_wm only
            for Gen12(Ville)
          - Some sagv debugs removed(Ville)
          - skl_print_wm_changes improvements(Ville)
          - Do assignment instead of memcpy in
            skl_pipe_wm_get_hw_state(Ville)
      
      v9: - Removed can_sagv variable(Ville)
          - Removed spurious line(Ville)
          - Changed u32 to unsigned int as agreed(Ville)
          - Assign sagv only for gen12 in
            skl_pipe_wm_get_hw_state(Ville)
      Signed-off-by: NStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
      [vsyrjala: Remove the dead 'return false' from intel_crtc_can_enable_sagv()]
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20200514074853.9508-2-stanislav.lisovskiy@intel.com
      7241c57d
  2. 14 5月, 2020 4 次提交
  3. 09 5月, 2020 1 次提交
  4. 04 5月, 2020 1 次提交
  5. 24 4月, 2020 3 次提交
  6. 21 4月, 2020 4 次提交
  7. 18 4月, 2020 2 次提交
  8. 16 4月, 2020 2 次提交
  9. 04 4月, 2020 6 次提交
  10. 28 3月, 2020 4 次提交
  11. 27 3月, 2020 1 次提交
  12. 26 3月, 2020 3 次提交
  13. 20 3月, 2020 1 次提交
    • V
      drm/i915: Fix crtc nv12 etc. plane bitmasks for DPMS off · cb1824bb
      Ville Syrjälä 提交于
      We only consider crtc_state->enable when initially calculating plane
      visibility. Later on we try to override the plane's state to invisible
      if the crtc is in DPMS off state (crtc_state->active==false).
      Unfortunately the code doing that only updates the plane_state.visible
      flag and the crtc_state.active_planes bimask, but forgets to update
      some of the other plane bitmasks stored in the crtc_state. Namely
      crtc_state.nv12_planes is left set up based on the original visibility
      check which makes icl_check_nv12_planes() pick a slave plane for the
      flagged plane in the bitmask. Later on we hit the watermark code
      which sees a plane with a slave assigned and it then makes the
      logical assumption that the master plane must itself be visible.
      Since the master's plane_state.visible flag was already cleared
      we get a WARN.
      
      Fix the problem by clearing all the plane bitmasks for DPMS off.
      This is more or less the wrong approach and instead we should
      calculate all the plane related state purely based crtc_state->enable
      (to guarantee that the subsequent DPMS on can't fail). However in
      the past we definitely had some roadblocks to making that happen.
      Not sure how many are left these days, but let's stick to the current
      approach since it's a much simpler fix to the immediate problem
      (the WARN).
      
      v2: Keep the visible=false, it's important (Rodrigo)
      
      Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20200318174515.31637-1-ville.syrjala@linux.intel.comReviewed-by: NRodrigo Vivi <rodrigo.vivi@intel.com>
      cb1824bb
  14. 03 3月, 2020 3 次提交
  15. 02 3月, 2020 1 次提交
  16. 28 2月, 2020 2 次提交
  17. 27 2月, 2020 1 次提交