1. 18 1月, 2015 1 次提交
    • M
      ARM: OMAP: Work around hardcoded interrupts · 0fb22a8f
      Marc Zyngier 提交于
      Commit 9a1091ef ("irqchip: gic: Support hierarchy irq domain")
      changed the GIC driver to use a non-legacy IRQ domain on DT
      platforms. This patch assumes that DT-driven systems are getting
      all of their interrupts from device tree.
      
      Turns out that OMAP has quite a few hidden gems, and still uses
      hardcoded interrupts despite having fairly complete DTs.
      
      This patch attempts to work around these by offering a translation
      method that can be called directly from the hwmod code, if present.
      The same hack is sprinkled over PRCM and TWL.
      
      It isn't pretty, but it seems to do the job without having to add
      more hacks to the interrupt controller code.
      
      Tested on OMAP4 (Panda-ES) and OMAP5 (UEVM5432).
      Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
      Acked-by: NNishanth Menon <nm@ti.com>
      [tony@atomide.com: updated to fix make randconfig issue]
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      0fb22a8f
  2. 06 1月, 2015 1 次提交
    • L
      ARM: omap5/dra7xx: Enable booting secondary CPU in HYP mode · 999f934d
      Lennart Sorensen 提交于
      If the boot loader enables HYP mode on the boot CPU, the secondary CPU
      also needs to call into the ROM to switch to HYP mode before booting.
      The firmwares on the omap5 and dra7xx unfortunately do not take care
      of this, so it has to be handled by the kernel.
      
      This patch is based on "[PATCH 2/2] ARM: OMAP5: Add HYP mode entry support
      for secondary CPUs" by Santosh Shilimkar <santosh.shilimkar@ti.com>,
      except this version does not require a compile time CONFIG to control
      if it should enable HYP mode or not, it simply does it based on the mode
      of the boot CPU, so it works whether the CPU boots in SVC or HYP mode,
      and should even work as a guest kernel inside kvm if qemu decides to
      support emulating the omap5 or dra7xx.
      
      Cc: stable@vger.kernel.org #v3.16+
      Signed-off-by: NLen Sorensen <lsorense@csclub.uwaterloo.ca>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      999f934d
  3. 17 9月, 2014 1 次提交
    • F
      irqchip: add irq-omap-intc.h header · eaacabc0
      Felipe Balbi 提交于
      OMAP INTC irqchip driver will be moved under
      drivers/irqchip/ soon but we still have a dependency
      with mach-omap2 when it comes to idle functions.
      
      In order to make it easy to share those function
      prototypes with OMAP PM code, we introduce this new
      header.
      
      To avoid modifying several board-files and some of
      the PM-related code, we just include the new header
      from common.h which was already included by all
      users of IRQ-related PM code.
      Signed-off-by: NFelipe Balbi <balbi@ti.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      eaacabc0
  4. 12 9月, 2014 5 次提交
  5. 09 9月, 2014 2 次提交
  6. 07 7月, 2014 1 次提交
  7. 17 6月, 2014 1 次提交
    • A
      ARM: omap2: fix am43xx dependency on l2x0 cache · 2ad501cc
      Arnd Bergmann 提交于
      Commit d941f86f ("ARM: l2c: AM43x: add L2 cache support") enabled
      the L2 cache support for the am43xx SoC, but caused a build regression
      when the driver for that cache controller is disabled:
      
      arch/arm/mach-omap2/built-in.o: In function `am43xx_init_early':
      :(.init.text+0xb20): undefined reference to `omap_l2_cache_init'
      
      This did not happen for OMAP4, which has the same call, but enables
      the l2x0 driver unconditionally. We could do the same thing for
      am43xx, but it seems better to allow turning it off and make the
      code work in either case.
      
      This adds an inline wrapper for omap_l2_cache_init for the disabled
      case, and removes the 'select' from OMAP4 so it becomes a user
      visible option.
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      Acked-by: NTony Lindgren <tony@atomide.com>
      Cc: linux-omap@vger.kernel.org
      2ad501cc
  8. 16 6月, 2014 1 次提交
  9. 30 5月, 2014 1 次提交
  10. 19 3月, 2014 2 次提交
    • T
      ARM: OMAP2+: DT 'compatible' tweak for displays · 6a0e6b38
      Tomi Valkeinen 提交于
      As there is no common panel framework in the kernel, we have OMAP
      specific panel drivers. However, the DT data should be generic. This
      brings the issue that some other platform could use the same panels, and
      would need to create a driver with the same 'compatible' string as the
      OMAP driver.
      
      In the long run, we have to get a common panel framework. For the time
      being, this patch solves the issue:
      
      At early boot time, we go through the DT nodes looking for the panels
      the kernel supports for OMAP. For each found node, the 'compatible'
      string is prepended with "omapdss,", i.e. "sony,acx565akm" becomes
      "omapdss,sony,acx565akm". The OMAP display drivers all have "omapdss,"
      at the beginning of their compatible field.
      
      This allows us to have generic DT data, but OMAP specific display
      drivers.
      Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      Reviewed-by: NArchit Taneja <archit@ti.com>
      Acked-by: NTony Lindgren <tony@atomide.com>
      6a0e6b38
    • T
      ARM: OMAP2+: add omapdss_init_of() · dcdf407b
      Tomi Valkeinen 提交于
      The OMAP display architecture requires a bunch of platform devices which
      are not created via .dts (for now). We also need to pass a few function
      pointers and the DSS hardware version from the arch code to omapdss
      driver.
      
      This patch adds omapdss_init_of() function, called from board-generic at
      init time, which handles those tasks.
      Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
      Reviewed-by: NArchit Taneja <archit@ti.com>
      Acked-by: NTony Lindgren <tony@atomide.com>
      dcdf407b
  11. 01 2月, 2014 2 次提交
  12. 18 1月, 2014 1 次提交
  13. 09 12月, 2013 1 次提交
    • T
      ARM: OMAP2+: Add support for legacy auxdata for twl · dad12d11
      Tony Lindgren 提交于
      As we currently need to support a mix of legacy platform data and
      device tree intialized data, let's make sure things keep working
      for the TWL GPIOs.
      
      Mostly the issue is caused by the fact that DSS does not yet have
      device tree bindings, so we need to rely on the TWL GPIO callback
      for setting up things like LCD backlight for some boards.
      
      As of_platform_populate() for the TWL GPIO is called by twl-core
      after the I2C bus has been initialized, we cannot pass the auxdata
      table from the board init code to twl-core like we used to with
      just legacy platform data.
      
      So let's use the omap_device bus hook to patch in the platform
      data for TWL GPIO until we have sorted out the issues with the
      TWL GPIOs and device tree bindings.
      
      The other option was be to initialize twl core using legacy
      platform data, which seems like a step backwards as we're moving
      to device tree only initialization.  And we really don't want to
      add custom configuration functions to the TWL GPIO driver either
      for this.
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      dad12d11
  14. 19 11月, 2013 1 次提交
  15. 22 10月, 2013 1 次提交
    • N
      ARM: OMAP2+: add missing lateinit hook for calling pm late init · 765e7a06
      Nishanth Menon 提交于
      AM335x, AM43xx, OMAP5 and DRA7 have missing late init hook. Introduce
      SoC specific hook with a call to OMAP2+ generic lateinit hook. This
      allows the generic late initializations such as cpufreq hooks to be
      active.
      
      Based on out-of-tree patches that need to be introduced in
      mainline, this introduction allows us to provide the foundation for
      further SoC specific features as they are developed.
      
      Cc: Benoit Cousson <bcousson@baylibre.com>
      Cc: Kevin Hilman <khilman@deeprootsystems.com>
      Cc: Paul Walmsley <paul@pwsan.com>
      Cc: Tony Lindgren <tony@atomide.com>
      Signed-off-by: NNishanth Menon <nm@ti.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      765e7a06
  16. 11 10月, 2013 1 次提交
  17. 26 9月, 2013 1 次提交
  18. 13 8月, 2013 1 次提交
  19. 10 7月, 2013 1 次提交
  20. 12 6月, 2013 1 次提交
    • A
      ARM: OMAP2+: AM43x: early init · c5107027
      Afzal Mohammed 提交于
      Minimal early init - PRCM initialization not yet taken care.
      
      Control module is similar (base address, feature register etc.) as
      that of AM335x, while PRCM base address is different. Instead of
      adding a new header file for AM43x, PRCM base address is added in
      AM335x header file as it is similar to it to a large extent.
      Signed-off-by: NAfzal Mohammed <afzal@ti.com>
      [tony@atomide.com: updated to drop am33xx_check_features()]
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      c5107027
  21. 10 4月, 2013 2 次提交
  22. 09 4月, 2013 1 次提交
  23. 02 4月, 2013 1 次提交
  24. 27 3月, 2013 1 次提交
    • R
      ARM: OMAP: clocks: Delay clk inits atleast until slab is initialized · ff931c82
      Rajendra Nayak 提交于
      clk inits on OMAP happen quite early, even before slab is available.
      The dependency comes from the fact that the timer init code starts to
      use clocks and hwmod and we need clocks to be initialized by then.
      
      There are various problems doing clk inits this early, one is,
      not being able to do dynamic clk registrations and hence the
      dependency on clk-private.h. The other is, inability to debug
      early kernel crashes without enabling DEBUG_LL and earlyprintk.
      
      Doing early clk init also exposed another instance of a kernel
      panic due to a BUG() when CONFIG_DEBUG_SLAB is enabled.
      
      [    0.000000] Kernel BUG at c01174f8 [verbose debug info unavailable]
      [    0.000000] Internal error: Oops - BUG: 0 [#1] SMP ARM
      [    0.000000] Modules linked in:
      [    0.000000] CPU: 0    Not tainted  (3.9.0-rc1-12179-g72d48f9 #6)
      [    0.000000] PC is at __kmalloc+0x1d4/0x248
      [    0.000000] LR is at __clk_init+0x2e0/0x364
      [    0.000000] pc : [<c01174f8>]    lr : [<c0441f54>]    psr: 600001d3
      [    0.000000] sp : c076ff28  ip : c065cefc  fp : c0441f54
      [    0.000000] r10: 0000001c  r9 : 000080d0  r8 : c076ffd4
      [    0.000000] r7 : c074b578  r6 : c0794d88  r5 : 00000040  r4 : 00000000
      [    0.000000] r3 : 00000000  r2 : c07cac70  r1 : 000080d0  r0 : 0000001c
      [    0.000000] Flags: nZCv  IRQs off  FIQs off  Mode SVC_32  ISA ARM  Segment kernel
      [    0.000000] Control: 10c53c7d  Table: 8000404a  DAC: 00000017
      [    0.000000] Process swapper (pid: 0, stack limit = 0xc076e240)
      [    0.000000] Stack: (0xc076ff28 to 0xc0770000)
      [    0.000000] ff20:                   22222222 c0794ec8 c06546e8 00000000 00000040 c0794d88
      [    0.000000] ff40: c074b578 c076ffd4 c07951c8 c076e000 00000000 c0441f54 c074b578 c076ffd4
      [    0.000000] ff60: c0793828 00000040 c0794d88 c074b578 c076ffd4 c0776900 c076e000 c07272ac
      [    0.000000] ff80: 2f800000 c074c968 c07f93d0 c0719780 c076ffa0 c076ff98 00000000 00000000
      [    0.000000] ffa0: 00000000 00000000 00000000 00000001 c074cd6c c077b1ec 8000406a c0715724
      [    0.000000] ffc0: 00000000 00000000 00000000 00000000 00000000 c074c968 10c53c7d c0776974
      [    0.000000] ffe0: c074cd6c c077b1ec 8000406a 411fc092 00000000 80008074 00000000 00000000
      [    0.000000] [<c01174f8>] (__kmalloc+0x1d4/0x248) from [<c0441f54>] (__clk_init+0x2e0/0x364)
      [    0.000000] [<c0441f54>] (__clk_init+0x2e0/0x364) from [<c07272ac>] (omap4xxx_clk_init+0xbc/0x140)
      [    0.000000] [<c07272ac>] (omap4xxx_clk_init+0xbc/0x140) from [<c0719780>] (setup_arch+0x15c/0x284)
      [    0.000000] [<c0719780>] (setup_arch+0x15c/0x284) from [<c0715724>] (start_kernel+0x7c/0x334)
      [    0.000000] [<c0715724>] (start_kernel+0x7c/0x334) from [<80008074>] (0x80008074)
      [    0.000000] Code: e5883004 e1a00006 e28dd00c e8bd8ff0 (e7f001f2)
      [    0.000000] ---[ end trace 1b75b31a2719ed1c ]---
      [    0.000000] Kernel panic - not syncing: Attempted to kill the idle task!
      
      It was a know issue, that slab allocations would fail when common
      clock core tries to cache parent pointers for mux clocks on OMAP,
      and hence a patch 'clk: Allow late cache allocation for clk->parents,
      commit 7975059d' was added to work this problem around.
      A BUG() within kmalloc() with CONFIG_DEBUG_SLAB enabled was completely
      overlooked causing this regression.
      
      More details on the issue reported can be found here,
      http://www.mail-archive.com/linux-omap@vger.kernel.org/msg85932.html
      
      With all these issues around clk inits happening way too early, it
      makes sense to at least move them to a point where dynamic memory
      allocations are possible. So move them to a point just before the
      timer code starts using clocks and hwmod.
      
      This should at least pave way for clk inits on OMAP moving to dynamic
      clock registrations instead of using the static macros defined in
      clk-private.h.
      
      The issue with kernel panic while CONFIG_DEBUG_SLAB is enabled
      was reported by Piotr Haber and Tony Lindgren and this patch
      fixes the reported issue as well.
      Reported-by: NPiotr Haber <phaber@broadcom.com>
      Reported-by: NTony Lindgren <tony@atomide.com>
      Signed-off-by: NRajendra Nayak <rnayak@ti.com>
      Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
      Reviewed-by: NMike Turquette <mturquette@linaro.org>
      Acked-by: NPaul Walmsley <paul@pwsan.com>
      Cc: stable@vger.kernel.org  # v3.8
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      ff931c82
  25. 05 3月, 2013 1 次提交
  26. 02 2月, 2013 1 次提交
  27. 25 12月, 2012 1 次提交
  28. 22 11月, 2012 1 次提交
  29. 09 11月, 2012 3 次提交
  30. 06 11月, 2012 1 次提交
    • C
      ARM: OMAP4: retrigger localtimers after re-enabling gic · cd8ce159
      Colin Cross 提交于
      'Workaround for ROM bug because of CA9 r2pX gic control'
      register change disables the gic distributor while the secondary
      cpu is being booted.  If a localtimer interrupt on the primary cpu
      occurs when the distributor is turned off, the interrupt is lost,
      and the localtimer never fires again.
      
      Make the primary cpu wait for the secondary cpu to reenable the
      gic distributor (with interrupts off for safety), and then
      check if the pending bit is set in the localtimer but not the
      gic.  If so, ack it in the localtimer, and reset the timer with
      the minimum timeout to trigger a new timer interrupt.
      Signed-off-by: NColin Cross <ccross@android.com>
      [s-jan@ti.com: adapted to k3.4 + validated functionality]
      Signed-off-by: NSebastien Jan <s-jan@ti.com>
      [t-kristo@ti.com: dropped generic ARM kernel exports from the code, rebased
       to mainline]
      Signed-off-by: NTero Kristo <t-kristo@ti.com>
      Signed-off-by: NKevin Hilman <khilman@ti.com>
      cd8ce159