1. 11 8月, 2017 3 次提交
    • B
      drm/i915: Add format modifiers for Intel · 714244e2
      Ben Widawsky 提交于
      This was based on a patch originally by Kristian. It has been modified
      pretty heavily to use the new callbacks from the previous patch.
      
      v2:
        - Add LINEAR and Yf modifiers to list (Ville)
        - Combine i8xx and i965 into one list of formats (Ville)
        - Allow 1010102 formats for Y/Yf tiled (Ville)
      
      v3:
        - Handle cursor formats (Ville)
        - Put handling for LINEAR in the mod_support functions (Ville)
      
      v4:
        - List each modifier explicitly in supported modifiers (Ville)
        - Handle the CURSOR plane (Ville)
      
      v5:
        - Split out cursor and sprite handling (Ville)
      
      v6:
        - Actually use the sprite funcs (Emil)
        - Use unreachable (Emil)
      
      v7:
        - Only allow Intel modifiers and LINEAR (Ben)
      
      v8
        - Fix spite assert introduced in v6 (Daniel)
      
      v9
        - Change vendor check logic to avoid magic 56 (Emil)
        - Reorder skl_mod_support (Ville)
        - make intel_plane_funcs static, could be done as of v5 (Ville)
        - rename local variable intel_format_modifiers to modifiers (Ville)
          - actually use sprite modifiers
        - split out modifier/formats by platform (Ville)
      
      v10:
        - Undo vendor check from v9
      
      v11:
        - Squash CCS advertisement into this patch (daniels)
        - Don't advertise CCS on higher sprite planes (daniels)
      
      v12:
        - Don't advertise Y-tiled or CCS on any sprite planes, since we don't
          allocate enough DDB space for it to work. (daniels)
      
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com> (v8)
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: NDaniel Stone <daniels@collabora.com>
      714244e2
    • V
      drm/i915: Add render decompression support · 2e2adb05
      Ville Syrjälä 提交于
      SKL+ display engine can scan out certain kinds of compressed surfaces
      produced by the render engine. This involved telling the display engine
      the location of the color control surfae (CCS) which describes
      which parts of the main surface are compressed and which are not. The
      location of CCS is provided by userspace as just another plane with its
      own offset.
      
      Add the required stuff to validate the user provided AUX plane metadata
      and convert the user provided linear offset into something the hardware
      can consume.
      
      Due to hardware limitations we require that the main surface and
      the AUX surface (CCS) be part of the same bo. The hardware also
      makes life hard by not allowing you to provide separate x/y offsets
      for the main and AUX surfaces (excpet with NV12), so finding suitable
      offsets for both requires a bit of work. Assuming we still want keep
      playing tricks with the offsets. I've just gone with a dumb "search
      backward for suitable offsets" approach, which is far from optimal,
      but it works.
      
      Also not all planes will be capable of scanning out compressed surfaces,
      and eg. 90/270 degree rotation is not supported in combination with
      decompression either.
      
      This patch may contain work from at least the following people:
      * Vandana Kannan <vandana.kannan@intel.com>
      * Daniel Vetter <daniel@ffwll.ch>
      * Ben Widawsky <ben@bwidawsk.net>
      
      v2: Deal with display workarounds 0390, 0531, 1125 (Paulo)
      v3: Pretend CCS tiles are regular 128 byte wide Y tiles (Jason)
          Put the AUX register defines to the correct place
          Fix up the slightly bogus rotation check
      v4: Use I915_WRITE_FW() due to plane update locking changes
          s/return -EINVAL/goto err/ in intel_framebuffer_init()
          Eliminate a bunch hardcoded numbers in CCS code
      
      v5: (By Ben)
      conflict resolution +
      -               res_blocks += fixed_16_16_to_u32_round_up(y_tile_minimum);
      +               res_blocks += fixed16_to_u32_round_up(y_tile_minimum);
      
      v6: (daniels) Fix botched commit message.
      
      Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
      Cc: Daniel Vetter <daniel@ffwll.ch>
      Cc: Ben Widawsky <ben@bwidawsk.net>
      Cc: Jason Ekstrand <jason@jlekstrand.net>
      Signed-off-by: NVille Syrjä <ville.syrjala@linux.intel.com>
      Reviewed-by: Ben Widawsky <ben@bwidawsk.net> (v1)
      Reviewed-by: NDaniel Stone <daniels@collabora.com>
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: NDaniel Stone <daniels@collabora.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/20170801165817.7063-1-ben@bwidawsk.net
      2e2adb05
    • V
      drm/i915: Implement .get_format_info() hook for CCS · bbfb6ce8
      Ville Syrjälä 提交于
      SKL+ display engine can scan out certain kinds of compressed surfaces
      produced by the render engine. This involved telling the display engine
      the location of the color control surfae (CCS) which describes which
      parts of the main surface are compressed and which are not. The location
      of CCS is provided by userspace as just another plane with its own offset.
      
      By providing our own format information for the CCS formats, we should
      be able to make framebuffer_check() do the right thing for the CCS
      surface as well.
      
      Note that we'll return the same format info for both Y and Yf tiled
      format as that's what happens with the non-CCS Y vs. Yf as well. If
      desired, we could potentially return a unique pointer for each
      pixel_format+tiling+ccs combination, in which case we immediately be
      able to tell if any of that stuff changed by just comparing the
      pointers. But that does sound a bit wasteful space wise.
      
      v2: Drop the 'dev' argument from the hook
      v3: Include the description of the CCS surface layout
      v4: Pretend CCS tiles are regular 128 byte wide Y tiles (Jason)
      v5: Re-drop 'dev', fix commit message, add missing drm_fourcc.h
          description of CCS layout. (daniels)
      
      Cc: Daniel Vetter <daniel@ffwll.ch>
      Cc: Ben Widawsky <ben@bwidawsk.net>
      Cc: Jason Ekstrand <jason@jlekstrand.net>
      Acked-by: NJason Ekstrand <jason@jlekstrand.net>
      Reviewed-by: Ben Widawsky <ben@bwidawsk.net> (v3)
      Reviewed-by: NDaniel Stone <daniels@collabora.com>
      Signed-off-by: NVille Syrjä <ville.syrjala@linux.intel.com>
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: NDaniel Stone <daniels@collabora.com>
      bbfb6ce8
  2. 10 8月, 2017 2 次提交
  3. 09 8月, 2017 1 次提交
  4. 08 8月, 2017 7 次提交
  5. 05 8月, 2017 1 次提交
  6. 04 8月, 2017 12 次提交
  7. 03 8月, 2017 1 次提交
  8. 02 8月, 2017 2 次提交
    • M
      drm/i915: Fix out-of-bounds array access in bdw_load_gamma_lut · 09a92bc8
      Maarten Lankhorst 提交于
      bdw_load_gamma_lut is writing beyond the array to the maximum value.
      The intend of the function is to clamp values > 1 to 1, so write
      the intended color to the max register.
      
      This fixes the following KASAN warning:
      
      [  197.020857] [IGT] kms_pipe_color: executing
      [  197.063434] [IGT] kms_pipe_color: starting subtest ctm-0-25-pipe0
      [  197.078989] ==================================================================
      [  197.079127] BUG: KASAN: slab-out-of-bounds in bdw_load_gamma_lut.isra.2+0x3b9/0x570 [i915]
      [  197.079188] Read of size 2 at addr ffff8800d38db150 by task kms_pipe_color/1839
      [  197.079208] CPU: 2 PID: 1839 Comm: kms_pipe_color Tainted: G     U 4.13.0-rc1-patser+ #5211
      [  197.079215] Hardware name: NUC5i7RYB, BIOS RYBDWi35.86A.0246.2015.0309.1355 03/09/2015
      [  197.079220] Call Trace:
      [  197.079230]  dump_stack+0x68/0x9e
      [  197.079239]  print_address_description+0x6f/0x250
      [  197.079251]  kasan_report+0x216/0x370
      [  197.079374]  ? bdw_load_gamma_lut.isra.2+0x3b9/0x570 [i915]
      [  197.079451]  ? gen8_write16+0x4e0/0x4e0 [i915]
      [  197.079460]  __asan_report_load2_noabort+0x14/0x20
      [  197.079535]  bdw_load_gamma_lut.isra.2+0x3b9/0x570 [i915]
      [  197.079612]  broadwell_load_luts+0x1df/0x550 [i915]
      [  197.079690]  intel_color_load_luts+0x7b/0x80 [i915]
      [  197.079764]  intel_begin_crtc_commit+0x138/0x760 [i915]
      [  197.079783]  drm_atomic_helper_commit_planes_on_crtc+0x1a3/0x820 [drm_kms_helper]
      [  197.079859]  ? intel_pre_plane_update+0x571/0x580 [i915]
      [  197.079937]  intel_update_crtc+0x238/0x330 [i915]
      [  197.080016]  intel_update_crtcs+0x10f/0x210 [i915]
      [  197.080092]  intel_atomic_commit_tail+0x1552/0x3340 [i915]
      [  197.080101]  ? _raw_spin_unlock+0x3c/0x40
      [  197.080110]  ? __queue_work+0xb40/0xbf0
      [  197.080188]  ? skl_update_crtcs+0xc00/0xc00 [i915]
      [  197.080195]  ? trace_hardirqs_on+0xd/0x10
      [  197.080269]  ? intel_atomic_commit_ready+0x128/0x13c [i915]
      [  197.080329]  ? __i915_sw_fence_complete+0x5b8/0x6d0 [i915]
      [  197.080336]  ? debug_object_activate+0x39e/0x580
      [  197.080397]  ? i915_sw_fence_await+0x30/0x30 [i915]
      [  197.080409]  ? __might_sleep+0x15b/0x180
      [  197.080483]  intel_atomic_commit+0x944/0xa70 [i915]
      [  197.080490]  ? refcount_dec_and_test+0x11/0x20
      [  197.080567]  ? intel_atomic_commit_tail+0x3340/0x3340 [i915]
      [  197.080597]  ? drm_atomic_crtc_set_property+0x303/0x580 [drm]
      [  197.080674]  ? intel_atomic_commit_tail+0x3340/0x3340 [i915]
      [  197.080704]  drm_atomic_commit+0xd7/0xe0 [drm]
      [  197.080722]  drm_atomic_helper_crtc_set_property+0xec/0x130 [drm_kms_helper]
      [  197.080749]  drm_mode_crtc_set_obj_prop+0x7d/0xb0 [drm]
      [  197.080775]  drm_mode_obj_set_property_ioctl+0x50b/0x5d0 [drm]
      [  197.080783]  ? __might_fault+0x104/0x180
      [  197.080809]  ? drm_mode_obj_find_prop_id+0x160/0x160 [drm]
      [  197.080838]  ? drm_mode_obj_find_prop_id+0x160/0x160 [drm]
      [  197.080861]  drm_ioctl_kernel+0x154/0x1a0 [drm]
      [  197.080885]  drm_ioctl+0x624/0x8f0 [drm]
      [  197.080910]  ? drm_mode_obj_find_prop_id+0x160/0x160 [drm]
      [  197.080934]  ? drm_getunique+0x210/0x210 [drm]
      [  197.080943]  ? __handle_mm_fault+0x1bd0/0x1ce0
      [  197.080949]  ? lock_downgrade+0x610/0x610
      [  197.080957]  ? __lru_cache_add+0x15a/0x180
      [  197.080967]  do_vfs_ioctl+0xd92/0xe40
      [  197.080975]  ? ioctl_preallocate+0x1b0/0x1b0
      [  197.080982]  ? selinux_capable+0x20/0x20
      [  197.080991]  ? __do_page_fault+0x7b7/0x9a0
      [  197.080997]  ? lock_downgrade+0x5bb/0x610
      [  197.081007]  ? security_file_ioctl+0x57/0x90
      [  197.081016]  SyS_ioctl+0x4e/0x80
      [  197.081024]  entry_SYSCALL_64_fastpath+0x18/0xad
      [  197.081030] RIP: 0033:0x7f61f287a987
      [  197.081035] RSP: 002b:00007fff7d44d188 EFLAGS: 00000246 ORIG_RAX: 0000000000000010
      [  197.081043] RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007f61f287a987
      [  197.081048] RDX: 00007fff7d44d1c0 RSI: 00000000c01864ba RDI: 0000000000000003
      [  197.081053] RBP: 00007f61f2b3eb00 R08: 0000000000000059 R09: 0000000000000000
      [  197.081058] R10: 0000002ea5c4a290 R11: 0000000000000246 R12: 00007f61f2b3eb58
      [  197.081063] R13: 0000000000001010 R14: 00007f61f2b3eb58 R15: 0000000000002702
      
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101659Signed-off-by: NMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Reported-by: NMartin Peres <martin.peres@linux.intel.com>
      Cc: Martin Peres <martin.peres@linux.intel.com>
      Fixes: 82cf435b ("drm/i915: Implement color management on bdw/skl/bxt/kbl")
      Cc: Shashank Sharma <shashank.sharma@intel.com>
      Cc: Kiran S Kumar <kiran.s.kumar@intel.com>
      Cc: Kausal Malladi <kausalmalladi@gmail.com>
      Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
      Cc: Matt Roper <matthew.d.roper@intel.com>
      Cc: Daniel Vetter <daniel.vetter@intel.com>
      Cc: Jani Nikula <jani.nikula@linux.intel.com>
      Cc: intel-gfx@lists.freedesktop.org
      Cc: <stable@vger.kernel.org> # v4.7+
      Link: https://patchwork.freedesktop.org/patch/msgid/20170724091431.24251-1-maarten.lankhorst@linux.intel.comReviewed-by: NLionel Landwerlin <lionel.g.landwerlin@intel.com>
      09a92bc8
    • B
      drm: Plumb modifiers through plane init · e6fc3b68
      Ben Widawsky 提交于
      This is the plumbing for supporting fb modifiers on planes. Modifiers
      have already been introduced to some extent, but this series will extend
      this to allow querying modifiers per plane. Based on this, the client to
      enable optimal modifications for framebuffers.
      
      This patch simply allows the DRM drivers to initialize their list of
      supported modifiers upon initializing the plane.
      
      v2: A minor addition from Daniel
      
      v3:
      * Updated commit message
      * s/INVALID/DRM_FORMAT_MOD_INVALID (Liviu)
      * Remove some excess newlines (Liviu)
      * Update comment for > 64 modifiers (Liviu)
      
      v4: Minor comment adjustments (Liviu)
      
      v5: Some new platforms added due to rebase
      
      v6: Add some missed plane inits (or maybe they're new - who knows at
      this point) (Daniel)
      Signed-off-by: NBen Widawsky <ben@bwidawsk.net>
      Reviewed-by: Daniel Stone <daniels@collabora.com> (v2)
      Reviewed-by: NLiviu Dudau <Liviu.Dudau@arm.com>
      Signed-off-by: NDaniel Stone <daniels@collabora.com>
      e6fc3b68
  9. 31 7月, 2017 1 次提交
  10. 28 7月, 2017 2 次提交
  11. 27 7月, 2017 8 次提交