- 02 6月, 2016 3 次提交
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由 Chen-Yu Tsai 提交于
Now the the HS-DDR mode clock timings have been corrected, we can re-enable these modes on the A80. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Chen-Yu Tsai 提交于
The MMC clock timings were incorrectly calculated, when the conversion from delay value to delay phase was done. The 50M DDR and 50M DDR 8bit timings are off, and make eMMC DDR unusable. Unfortunately it seems different controllers on the same SoC have different timings. The new settings are taken from mmc2, which is commonly used with eMMC. The settings for the slower timing modes seem to work despite being wrong, so leave them be. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Chen-Yu Tsai 提交于
When IS_ERR_VALUE was removed from the mmc core code, it was replaced with a simple not-zero check. This does not work, as the value checked is the return value for mmc_select_bus_width, which returns the set bit width on success. This made eMMC modes higher than HS-DDR unusable. Fix this by checking for a positive return value instead. Fixes: 287980e4 ("remove lots of IS_ERR_VALUE abuses") Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NHans de Goede <hdegoede@redhat.com> Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: NJaehoon Chung <jh80.chung@samsung.com> Reviewed-by: NShawn Lin <shawn.lin@rock-chips.com> Tested-by: NMarcel Ziswiler <marcel.ziswiler@toradex.com> Tested-by: NBjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 28 5月, 2016 1 次提交
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由 Arnd Bergmann 提交于
Most users of IS_ERR_VALUE() in the kernel are wrong, as they pass an 'int' into a function that takes an 'unsigned long' argument. This happens to work because the type is sign-extended on 64-bit architectures before it gets converted into an unsigned type. However, anything that passes an 'unsigned short' or 'unsigned int' argument into IS_ERR_VALUE() is guaranteed to be broken, as are 8-bit integers and types that are wider than 'unsigned long'. Andrzej Hajda has already fixed a lot of the worst abusers that were causing actual bugs, but it would be nice to prevent any users that are not passing 'unsigned long' arguments. This patch changes all users of IS_ERR_VALUE() that I could find on 32-bit ARM randconfig builds and x86 allmodconfig. For the moment, this doesn't change the definition of IS_ERR_VALUE() because there are probably still architecture specific users elsewhere. Almost all the warnings I got are for files that are better off using 'if (err)' or 'if (err < 0)'. The only legitimate user I could find that we get a warning for is the (32-bit only) freescale fman driver, so I did not remove the IS_ERR_VALUE() there but changed the type to 'unsigned long'. For 9pfs, I just worked around one user whose calling conventions are so obscure that I did not dare change the behavior. I was using this definition for testing: #define IS_ERR_VALUE(x) ((unsigned long*)NULL == (typeof (x)*)NULL && \ unlikely((unsigned long long)(x) >= (unsigned long long)(typeof(x))-MAX_ERRNO)) which ends up making all 16-bit or wider types work correctly with the most plausible interpretation of what IS_ERR_VALUE() was supposed to return according to its users, but also causes a compile-time warning for any users that do not pass an 'unsigned long' argument. I suggested this approach earlier this year, but back then we ended up deciding to just fix the users that are obviously broken. After the initial warning that caused me to get involved in the discussion (fs/gfs2/dir.c) showed up again in the mainline kernel, Linus asked me to send the whole thing again. [ Updated the 9p parts as per Al Viro - Linus ] Signed-off-by: NArnd Bergmann <arnd@arndb.de> Cc: Andrzej Hajda <a.hajda@samsung.com> Cc: Andrew Morton <akpm@linux-foundation.org> Link: https://lkml.org/lkml/2016/1/7/363 Link: https://lkml.org/lkml/2016/5/27/486 Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> # For nvmem part Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 23 5月, 2016 6 次提交
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由 Adrian Hunter 提交于
The CMD19/CMD14 bus width test has been found to be unreliable in some cases. It is not essential, so simply remove it. Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Adrian Hunter 提交于
The CMD19/CMD14 bus width test has been found to be unreliable in some cases. It is not essential, so simply remove it. Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Matt Gumbel 提交于
008GE0 Toshiba mmc in some Intel Baytrail tablets responds to MMC_SEND_EXT_CSD in 450-600ms. This patch will... () Increase the long read time quirk timeout from 300ms to 600ms. Original author of that quirk says 300ms was only a guess and that the number may need to be raised in the future. () Add this specific MMC to the quirk Signed-off-by: NMatt Gumbel <matthew.k.gumbel@intel.com> Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com> Cc: stable@vger.kernel.org Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Douglas Anderson 提交于
Historically for Rockchip devices we've relied on the power-on default (or perhaps the firmware setting) to get the correct drive phase for dw_mmc devices. This worked OK for the most part, but: * Relying on the setting just "being right" is a bit fragile. * As soon as there is an instance where the power on default is wrong or where the firmware didn't configure this properly then we'll get a mysterious failure. In commit 7a03fe6f ("clk: rockchip: reset init state before mmc card initialization") we actually started setting this explicitly in the kernel, but that commit wasn't quite right and also wasn't quite enough. See <https://patchwork.kernel.org/patch/9085311/> for some details. Let's explicitly set this phase in dw_mmc. The comments inside this patch try to explain the situation quite throughly, but the high level overview of this is: Before this patch on rk3288 devices tested (after revert of the clock patch described above): * eMMC: 180 degrees * SDMMC/SDIO0/SDIO1: 90 degrees After this patch: * Use 90 degree phase offset usually. * Use 180 degree phase offset for MMC_DDR52, SDR104, HS200. That means we are _changing_ behavior for those devices in this way: * If we have HS200 eMMC or DDR52 eMMC, we'll run ID mode at 90 degrees (vs 180) but otherwise have no change. * For any non-HS200 / non-DDR52 eMMC devices we'll now _always_ run at 90 degrees (vs 180). It seems fairly unlikely that building modern hardware is using an eMMC that isn't using DDR52 or HS200, of course. * For SDR104 cards we'll now run with 180 degree phase offset (vs 90). It's expected that 90 degree phase offset would have worked OK, but this gives us extra margin. I have tested this by inserting my collection of uSD cards (mostly UHS, though a few not) into a veyron_minnie and confirmed that they still seem to enumerate properly. For a subset of them I tried putting a filesystem on them and also tried running mmc_test. Fixes: 7a03fe6f ("clk: rockchip: reset init state before mmc card initialization") Signed-off-by: NDouglas Anderson <dianders@chromium.org> Reviewed-by: NShawn Lin <shawn.lin@rock-chips.com> Tested-by: NHeiko Stuebner <heiko@sntech.de> Tested-by: NEnric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Jaehoon Chung 提交于
According to DesignWare TRM, BLKSIZ is 16bits. Then it's correct that max_blk_size should be 0xFFFF, not 0x10000. Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> Reviewed-by: NShawn Lin <shawn.lin@rock-chips.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Shawn Lin 提交于
Add MMC_CAP_CMD23 for dw_mmc-rockchip, otherwise failing to create rpmb partition. With it, we can get rpmb successfully: mmc1: new HS200 MMC card at address 0001 mmcblk0: mmc1:0001 DS2016 14.7 GiB mmcblk0boot0: mmc1:0001 DS2016 partition 1 4.00 MiB mmcblk0boot1: mmc1:0001 DS2016 partition 2 4.00 MiB mmcblk0rpmb: mmc1:0001 DS2016 partition 3 4.00 MiB Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com> Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 20 5月, 2016 1 次提交
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由 Adrian Hunter 提交于
Some devices connected to the SDHCI controller may have separate enabling lines that are controlled through GPIO. These devices need to be powered on and enabled before probing. This is to ensure all devices connected can be seen by the controller. Note, for "stable" this patch depends on the following change: commit 78a898d0 ("ACPI / PM: Export acpi_device_fix_up_power()") Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com> Reported-and-tested-by: NLaszlo Fiat <laszlo.fiat@gmail.com> Cc: <stable@vger.kernel.org> # 4.5+ Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org> Reported-by: NLaszlo Fiat <laszlo.fiat@gmail.com> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=112571 Link: http://lkml.kernel.org/r/CA+7w51inLtQSr656bJvOjGG9oQWKYPXH+xxDPJKbeJ=CcrkS9Q@mail.gmail.com
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- 17 5月, 2016 3 次提交
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由 Adrian Hunter 提交于
Re-tuning is not possible when switched to the RPMB partition. However re-tuning should not be needed if re-tuning is done immediately before switching, a small set of operations is done, and then we immediately switch back to the main partition. A previous patch ensured that we immediately switch back to the main partition. This patch uses the new facility to "pause" re-tuning before switching to the RPMB partition, and to "unpause" it after switching from the RPMB partition. Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Adrian Hunter 提交于
In preparation to support the use of the RPMB partition with transfer modes that might require re-tuning, always switch back to the main area after RPMB access. RPMB is accessible only via IOCTL so only those paths are affected. Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Adrian Hunter 提交于
Re-tuning is not possible when switched to the RPMB partition. However re-tuning should not be needed if re-tuning is done immediately before switching, a small set of operations is done, and then we immediately switch back to the main partition. To ensure that re-tuning can't be done for a short while, add a facility to "pause" re-tuning. The existing facility to hold / release re-tuning is used but it also flags re-tuning as needed to cause re-tuning before the next command (which will be the switch to RPMB). We also need to "unpause" in the recovery path, which is catered for by adding it to mmc_retune_disable(). Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 16 5月, 2016 5 次提交
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由 Adrian Hunter 提交于
Some eMMCs set the partition switch timeout too low. Now typically eMMCs are considered a critical component (e.g. because they store the root file system) and consequently are expected to be reliable. Thus we can neglect the use case where eMMCs can't switch reliably and we might want a lower timeout to facilitate speedy recovery. Although we could employ a quirk for the cards that are affected (if we could identify them all), as described above, there is little benefit to having a low timeout, so instead simply set a minimum timeout. The minimum is set to 300ms somewhat arbitrarily - the examples that have been seen had a timeout of 10ms but were sometimes taking 60-70ms. Cc: stable@vger.kernel.org Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Wolfram Sang 提交于
Tested on a Salvator-X board with a Spectec SDW-823 WLAN card. Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Wolfram Sang 提交于
I have two SDIO WLAN cards which specify being SDIO Rev. 1.1 cards but their FUNCE tuple reports the smaller size of a Rev 1.0 card. So, enforce 1.0 on these cards to avoid reading the not present registers. They are not really used anyhow. My cards initialize properly after this patch. Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Ken Sumrall 提交于
Add some logging to make it clear just how the emmc timeout was handled. Signed-off-by: NKen Sumrall <ksumrall@android.com> [AmitP: cherry-picked this Android patch from aosp common kernel android-4.4] Signed-off-by: NAmit Pundir <amit.pundir@linaro.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Dong Aisheng 提交于
After commit d6463f170cf0 ("mmc: sdhci: Remove redundant runtime PM calls"), some of original sdhci_do_xx() function wrappers becomes meaningless, so remove them. Signed-off-by: NDong Aisheng <aisheng.dong@nxp.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 10 5月, 2016 2 次提交
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由 Dong Aisheng 提交于
mmc_select_hs200() and mmc_select_hs() will keep the timing as before if switch fails. So it's meaningless to print the failed switched mode outside based on the current host timing. Furthermore, the original print is wrong, it should be: pr_warn("%s: switch to %s failed\n", mmc_hostname(card->host), mmc_card_hs(card) ? "high-speed" : (mmc_card_hs200(card) ? "hs200" : "")); Since we already have error message in mmc_select_hs200(), simply remove it outside. Signed-off-by: NDong Aisheng <aisheng.dong@nxp.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Dong Aisheng 提交于
Currently MMC core will keep going if HS200/HS timing switch failed with -EBADMSG error by the assumption that the old timing is still valid. However, for mmc_select_hs200 case, the signal voltage may have already been switched. If the timing switch failed, we should fall back to the old voltage in case the card is continue run with legacy timing. If fall back signal voltage failed, we explicitly report an EIO error to force retry during the next power cycle. Signed-off-by: NDong Aisheng <aisheng.dong@nxp.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 04 5月, 2016 9 次提交
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由 Shawn Lin 提交于
commit 61b914eb81f8 ("mmc: sdhci-of-arasan: add phy support for sdhci-of-arasan") introduce phy support for arasan. According to the vendor's databook, we should make sure the phy is in poweroff status before we configure the clk stuff. Otherwise it may cause some IO sample timing issues from the test. And we don't need this extra operation while running in low performance mode since phy doesn't trigger sampling block. Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Peter Ujfalusi 提交于
With the new dma_request_chan() the client driver does not need to look for the DMA resource and it does not need to pass filter_fn anymore. By switching to the new API the driver can now support deferred probing against DMA. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> CC: Ulf Hansson <ulf.hansson@linaro.org> CC: Jarkko Nikula <jarkko.nikula@bitmer.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Adrian Hunter 提交于
CMD0 or hardware reset may invalidate the cache, so it needs to be flushed before reset. In the case of recovery, we can't expect flushing the cache to work always, but have a go and ignore errors. Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Wolfram Sang 提交于
And return the old clock rate if something went wrong. Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Wolfram Sang 提交于
We had a regression on r8a7740 where the SDHI clock was a generic peripheral clock, so changing its rate was not desired. This should be fixed in the clock driver. However, it also shows that the new clock calculation should only be used on tested systems. Add a check for that. Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Wolfram Sang 提交于
RCar Gen2 and later implementations of TMIO/SDHI have their own set of features and additions. FAST_CLK_CHG is just one of them and I see a few others being added soon. Some may work on older chipsets but this needs to be tested case by case. Instead of adding a bunch of flags for each feature, add a global RCar2+ one for now. We can still break out features if the need arises. Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Wolfram Sang 提交于
Save a few lines, the codebase is large enough. Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Peter Ujfalusi 提交于
With the new dma_request_chan() the client driver does not need to look for the DMA resource and it does not need to pass filter_fn anymore. By switching to the new API the driver can now support deferred probing against DMA. Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Ludovic Desroches 提交于
The controller claims to support SDR104. In fact, it only supports a degraded SDR104 since the maximum frequency of the SD clock is 120 MHz instead of 208 MHz. The sdhci core is unaware of it and will compute a wrong clock divider. We can deal with this specific case by using presets. Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 02 5月, 2016 10 次提交
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由 Lars Persson 提交于
Some boards need different pin drive strength for the UHS mode. Add an optional pinctrl setting with two pin states covering UHS speeds and other speeds. Signed-off-by: NLars Persson <larper@axis.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Lars Persson 提交于
Add a start_signal_voltage_switch() operation to support enabling of UHS modes. Signed-off-by: NLars Persson <larper@axis.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Lars Persson 提交于
The driver in its current form does not support UHS at all due to a missing start_signal_voltage_switch callback. Also when this callback is added we should let the device tree control UHS capabilities using the standard mmc bindings. Signed-off-by: NLars Persson <larper@axis.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Wolfram Sang 提交于
Now that reading CTL_STATUS is consistent, we can remove CTL_STATUS2 and document how this is handled internally. Reviewed-by: NSimon Horman <horms+renesas@verge.net.au> Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Wolfram Sang 提交于
This bit has a different meaning in SDHI and original TMIO. Document that and use the proper naming. Reviewed-by: NSimon Horman <horms+renesas@verge.net.au> Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Wolfram Sang 提交于
To prevent confusion, use the virtual u32 CTL_STATUS in card_busy() the same way as in other parts of this driver. Reviewed-by: NSimon Horman <horms+renesas@verge.net.au> Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Wolfram Sang 提交于
BIT() makes it easier to match the bits to the datasheet. This is especially important here, since some variants have different names in their datasheets (like with Renesas R-Car). Reviewed-by: NSimon Horman <horms+renesas@verge.net.au> Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Wolfram Sang 提交于
Looking at the backlogs, I am not the only one who missed that the above functions do not read u32 from one register, but create a virtual u32 from reading to adjacent u16 registers (which depending on 'bus_shift' can be up to 8 byte apart). Because this driver supports old hardware for which we don't have documentation, I first wrongly assumed there was a variant which had a few u32 registers. Let's give the functions more descriptive names to make it more obvious what is happening. Reviewed-by: NSimon Horman <horms+renesas@verge.net.au> Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Tony Lindgren 提交于
The legacy user space for n900 relies on the MMC slot names. Let's check if those are passed in pdata and use them. As this makes the DT booting compatible with legacy booting, we should be able to start dropping omap3 legacy booting support in v4.8. Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: linux-mmc@vger.kernel.org Signed-off-by: NTony Lindgren <tony@atomide.com> Tested-by: NIvaylo Dimitrov <ivo.g.dimitrov.75@gmail.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Wolfram Sang 提交于
There is no support for this platform in the kernel anymore. Reported-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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