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  1. 06 6月, 2019 12 次提交
    • S
      arm64: dts: renesas: r8a77990: Add dynamic power coefficient · 70c6d23e
      由 Simon Horman 提交于 
      Describe the dynamic power coefficient of A53 CPUs.

Based on work by Gaku Inami <gaku.inami.xw@bp.renesas.com> and others.
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
      70c6d23e
    • D
      arm64: dts: renesas: r8a77990: Create thermal zone to support IPA · 8fa7d18f
      由 Dien Pham 提交于 
      Setup a thermal zone driven by SoC temperature sensor.
Create passive trip points and bind them to CPUFreq cooling
device that supports power extension.

In R-Car Gen3, IPA is supported for only one channel
Reason:
  Currently, IPA controls base on only CPU temperature.
  And only one thermal channel is assembled closest
  CPU cores is selected as target of IPA.
  If other channels are used, IPA controlling is not properly.

A single cooling device is described for all A53 CPUs as this
reflects that physically there is only one cooling device present.

This patch improves on an earlier version by:

* Omitting cooling-max-level and cooling-min-level properties which
  are no longer present in mainline as of v4.17
* Removing an unused trip-point0 node sub-property from the trips
  property.
* Defers adding dynamic-power-coefficient properties to a separate patch as
  these are properties of the CPU.

The long signed-off by chain below reflects many revisions, mainly
internal, that this patch has been through.
Signed-off-by: NDien Pham <dien.pham.ry@renesas.com>
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
      8fa7d18f
    • S
      arm64: dts: renesas: r8a77965: Add dynamic power coefficient · eb2cd8c2
      由 Simon Horman 提交于 
      Describe the dynamic power coefficient of A57 and A53 CPUs.

Based on work by Gaku Inami <gaku.inami.xw@bp.renesas.com> and others.
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
      eb2cd8c2
    • D
      arm64: dts: renesas: r8a77965: Create thermal zone to support IPA · 7ec67edd
      由 Dien Pham 提交于 
      Setup a thermal zone driven by SoC temperature sensor.
Create passive trip points and bind them to CPUFreq cooling
device that supports power extension.

In R-Car Gen3, IPA is supported for only one channel
(on H3/M3/M3N SoCs, it is channel THS3). Reason:
  Currently, IPA controls base on only CPU temperature.
  And only one thermal channel is assembled closest
  CPU cores is selected as target of IPA.
  If other channels are used, IPA controlling is not properly.

The A57 cooling device supports 5 cooling states which can be categorised
as follows:

0 & 1) boost (clocking up)
2)     default
3 & 4) cooling (clocking down)

Currently the thermal framework assumes that the default is the minimum,
or in other words there is no provision for handling boost states.
So this patch only describes the upper 3 states, default and cooling.

A single cooling device is described for all A57 CPUs and a separate
cooling device is described for all A53 CPUs. This reflects that physically
there is only one cooling device present for each type of CPU.

This patch improves on an earlier version by:

* Omitting cooling-max-level and cooling-min-level properties which
  are no longer present in mainline as of v4.17
* Removing an unused trip-point0 node sub-property from the trips
  property.
* Using cooling-device indexes such that maximum refers to maximum cooling
  rather than the inverse.
* Defers adding dynamic-power-coefficient properties to a separate patch as
  these are properties of the CPU.

The long signed-off by chain below reflects many revisions, mainly
internal, that this patch has been through.
Signed-off-by: NDien Pham <dien.pham.ry@renesas.com>
Signed-off-by: NAn Huynh <an.huynh.uj@rvc.renesas.com>
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
      7ec67edd
    • S
      arm64: dts: renesas: r8a7796: Add dynamic power coefficient · 9fed1b89
      由 Simon Horman 提交于 
      Describe the dynamic power coefficient of A57 and A53 CPUs.

Based on work by Gaku Inami <gaku.inami.xw@bp.renesas.com> and others.
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
      9fed1b89
    • D
      arm64: dts: renesas: r8a7796: Create thermal zone to support IPA · 81022ecd
      由 Dien Pham 提交于 
      Setup a thermal zone driven by SoC temperature sensor.
Create passive trip points and bind them to CPUFreq cooling
device that supports power extension.

In R-Car Gen3, IPA is supported for only one channel
 (on H3/M3/M3N SoCs, it is channel THS3). Reason:
  Currently, IPA controls base on only CPU temperature.
  And only one thermal channel is assembled closest
  CPU cores is selected as target of IPA.
  If other channels are used, IPA controlling is not properly.

The A57 cooling device supports 5 cooling states which can be categorised
as follows:

0 & 1) boost (clocking up)
2)     default
3 & 4) cooling (clocking down)

Currently the thermal framework assumes that the default is the minimum,
or in other words there is no provision for handling boost states.
So this patch only describes the upper 3 states, default and cooling.

A single cooling device is described for all A57 CPUs and a separate
cooling device is described for all A53 CPUs. This reflects that physically
there is only one cooling device present for each type of CPU.

This patch improves on an earlier version by:

* Omitting cooling-max-level and cooling-min-level properties which
  are no longer present in mainline as of v4.17
* Removing an unused trip-point0 node sub-property from the trips
  property.
* Using cooling-device indexes such that maximum refers to maximum cooling
  rather than the inverse.
* Defers adding dynamic-power-coefficient properties to a separate patch as
  these are properties of the CPU.

The long signed-off by chain below reflects many revisions, mainly
internal, that this patch has been through.
Signed-off-by: NDien Pham <dien.pham.ry@renesas.com>
Signed-off-by: NHien Dang <hien.dang.eb@rvc.renesas.com>
Signed-off-by: NAn Huynh <an.huynh.uj@rvc.renesas.com>
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
      81022ecd
    • S
      arm64: dts: renesas: r8a7795: Add dynamic power coefficient · 47e1714a
      由 Simon Horman 提交于 
      Describe the dynamic power coefficient of A57 and A53 CPUs.

Based on work by Gaku Inami <gaku.inami.xw@bp.renesas.com> and others.
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
      47e1714a
    • D
      arm64: dts: renesas: r8a7795: Create thermal zone to support IPA · 15d8cd83
      由 Dien Pham 提交于 
      Setup a thermal zone driven by SoC temperature sensor.
Create passive trip points and bind them to CPUFreq cooling
device that supports power extension.

In R-Car Gen3, IPA is supported for only one channel
(on H3/M3/M3N SoCs, it is channel THS3). Reason:
  Currently, IPA controls base on only CPU temperature.
  And only one thermal channel is assembled closest
  CPU cores is selected as target of IPA.
  If other channels are used, IPA controlling is not properly.

The A5 cooling device supports 5 cooling states which can be categorised as
follows:

0 & 1) boost (clocking up)
2)     default
3 & 4) cooling (clocking down)

Currently the thermal framework assumes that the default is the minimum,
or in other words there is no provision for handling boost states.
So this patch only describes the upper 3 states, default and cooling.

A single cooling device is described for all A57 CPUs and a separate
cooling device is described for all A53 CPUs. This reflects that physically
there is only one cooling device present for each type of CPU.

This patch improves on an earlier version by:

* Omitting cooling-max-level and cooling-min-level properties which
  are no longer present in mainline as of v4.17
* Removing an unused trip-point0 node sub-property from the trips
  property.
* Using cooling-device indexes such that maximum refers to maximum cooling
  rather than the inverse.
* Defers adding dynamic-power-coefficient properties to a separate patch as
  these are properties of the CPU.

The long signed-off by chain below reflects many revisions, mainly
internal, that this patch has been through.
Signed-off-by: NDien Pham <dien.pham.ry@renesas.com>
Signed-off-by: NKeita Kobayashi <keita.kobayashi.ym@renesas.com>
Signed-off-by: NGaku Inami <gaku.inami.xw@bp.renesas.com>
Signed-off-by: NHien Dang <hien.dang.eb@rvc.renesas.com>
Signed-off-by: NAn Huynh <an.huynh.uj@rvc.renesas.com>
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
      15d8cd83
    • Y
      arm64: dts: renesas: Revise usb2_phy nodes and phys properties · 7794bd7e
      由 Yoshihiro Shimoda 提交于 
      Since the commit 233da2c9 ("dt-bindings: phy: rcar-gen3-phy-usb2:
Revise #phy-cells property") revised the #phy-cells, this patch follows
the updated document for R-Car Gen3 and RZ/A2 SoCs.
Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
      7794bd7e
    • T
      arm64: dts: renesas: ebisu: Remove renesas, no-ether-link property · 90d4fa39
      由 Takeshi Kihara 提交于 
      It is incorrect to specify the no-ether-link property for the AVB device on
the Ebisu board. This is because the property should only be used when a
board does not provide a proper AVB_LINK signal. However, the Ebisu board
does provide this signal.

As per 87c059e9 ("arm64: dts: renesas: salvator-x: Remove renesas,
no-ether-link property") this fixes a bug:

    Steps to reproduce:
    - start AVB TX stream (Using aplay via MSE),
    - disconnect+reconnect the eth cable,
    - after a reconnection the eth connection goes iteratively up/down
      without user interaction,
    - this may heal after some seconds or even stay for minutes.

    As the documentation specifies, the "renesas,no-ether-link" option
    should be used when a board does not provide a proper AVB_LINK signal.
    There is no need for this option enabled on RCAR H3/M3 Salvator-X/XS
    and ULCB starter kits since the AVB_LINK is correctly handled by HW.

    Choosing to keep or remove the "renesas,no-ether-link" option will have
    impact on the code flow in the following ways:
    - keeping this option enabled may lead to unexpected behavior since the
      RX & TX are enabled/disabled directly from adjust_link function
      without any HW interrogation,
    - removing this option, the RX & TX will only be enabled/disabled after
      HW interrogation. The HW check is made through the LMON pin in PSR
      register which specifies AVB_LINK signal value (0 - at low level;
      1 - at high level).

    In conclusion, the present change is also a safety improvement because
    it removes the "renesas,no-ether-link" option leading to a proper way
    of detecting the link state based on HW interrogation and not on
    software heuristic.

Fixes: 8441ef64 ("arm64: dts: renesas: r8a77990: ebisu: Enable EthernetAVB")
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
[simon: updated changelog]
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
      90d4fa39
    • R
      arm64: dts: renesas: r8a774c0: Clean up CPU compatibles · 11290c09
      由 Robin Murphy 提交于 
      Apparently this DTS crossed over with commit 31af04cd ("arm64: dts:
Remove inconsistent use of 'arm,armv8' compatible string") and missed
out on the cleanup, so put it right.
Signed-off-by: NRobin Murphy <robin.murphy@arm.com>
Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
      11290c09
    • M
      arm64: dts: renesas: Use ip=on for bootargs · b31b43c9
      由 Magnus Damm 提交于 
      Convert bootargs from ip=dhcp to ip=on
Signed-off-by: NMagnus Damm <damm+renesas@opensource.se>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
      b31b43c9
  3. 29 5月, 2019 2 次提交
  5. 20 5月, 2019 13 次提交
  7. 19 5月, 2019 1 次提交
  9. 18 5月, 2019 7 次提交
  11. 17 5月, 2019 5 次提交
    • T
      powerpc/cacheinfo: Remove double free · 672eaf37
      由 Tobin C. Harding 提交于 
      kfree() after kobject_put(). Who ever wrote this was on crack.

Fixes: 7e803979 ("powerpc/cacheinfo: Fix kobject memleak")
Signed-off-by: NTobin C. Harding <tobin@kernel.org>
Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      672eaf37
    • A
      powerpc/mm/hash: Fix get_region_id() for invalid addresses · c179976c
      由 Aneesh Kumar K.V 提交于 
      Accesses by userspace to random addresses outside the user or kernel
address range will generate an SLB fault. When we handle that fault we
classify the effective address into several classes, eg. user, kernel
linear, kernel virtual etc.

For addresses that are completely outside of any valid range, we
should not insert an SLB entry at all, and instead immediately an
exception.

In the past this was handled in two ways. Firstly we would check the
top nibble of the address (using REGION_ID(ea)) and that would tell us
if the address was user (0), kernel linear (c), kernel virtual (d), or
vmemmap (f). If the address didn't match any of these it was invalid.

Then for each type of address we would do a secondary check. For the
user region we check against H_PGTABLE_RANGE, for kernel linear we
would mask the top nibble of the address and then check the address
against MAX_PHYSMEM_BITS.

As part of commit 0034d395 ("powerpc/mm/hash64: Map all the kernel
regions in the same 0xc range") we replaced REGION_ID() with
get_region_id() and changed the masking of the top nibble to only mask
the top two bits, which introduced a bug.

Addresses less than (4 << 60) are still handled correctly, they are
either less than (1 << 60) in which case they are subject to the
H_PGTABLE_RANGE check, or they are correctly checked against
MAX_PHYSMEM_BITS.

However addresses from (4 << 60) to ((0xc << 60) - 1), are incorrectly
treated as kernel linear addresses in get_region_id(). Then the top
two bits are cleared by EA_MASK in slb_allocate_kernel() and the
address is checked against MAX_PHYSMEM_BITS, which it passes due to
the masking. The end result is we incorrectly insert SLB entries for
those addresses.

That is not actually catastrophic, having inserted the SLB entry we
will then go on to take a page fault for the address and at that point
we detect the problem and report it as a bad fault.

Still we should not be inserting those entries, or treating them as
kernel linear addresses in the first place. So fix get_region_id() to
detect addresses in that range and return an invalid region id, which
we cause use to not insert an SLB entry and directly report an
exception.

Fixes: 0034d395 ("powerpc/mm/hash64: Map all the kernel regions in the same 0xc range")
Signed-off-by: NAneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
[mpe: Drop change to EA_MASK for now, rewrite change log]
Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      c179976c
    • A
      riscv: fix locking violation in page fault handler · 8fef9900
      由 Andreas Schwab 提交于 
      When a user mode process accesses an address in the vmalloc area
do_page_fault tries to unlock the mmap semaphore when it isn't locked.
Signed-off-by: NAndreas Schwab <schwab@suse.de>
[Palmer: Duplicated code instead of a goto]
Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
      8fef9900
    • Y
      RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs · a967a289
      由 Yash Shah 提交于 
      The driver currently supports only SiFive FU540-C000 platform.

The initial version of L2 cache controller driver includes:
- Initial configuration reporting at boot up.
- Support for ECC related functionality.
Signed-off-by: NYash Shah <yash.shah@sifive.com>
Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
      a967a289
    • P
      RISC-V: Avoid using invalid intermediate translations · 4c3aeb82
      由 Palmer Dabbelt 提交于 
      This is almost entirely a comment.
Signed-off-by: NPalmer Dabbelt <palmer@sifive.com>
Reviewed-by: NAnup Patel <anup@brainfault.org>
      4c3aeb82