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  1. 21 4月, 2021 1 次提交
  3. 14 4月, 2021 4 次提交
  5. 29 3月, 2021 2 次提交
  7. 25 3月, 2021 1 次提交
  9. 24 3月, 2021 1 次提交
    • M
      drm/i915: Add DISPLAY_VER() and related macros · 01eb15c9
      由 Matt Roper 提交于 
      Although we've long referred to platforms by a single "GEN" number, the
hardware teams have recommended that we stop doing this since the
various component IP blocks are going to start using independent number
schemes with varying cadence.  To support this, hardware platforms a bit
down the road are going to start providing MMIO registers that the
driver can read to obtain the "graphics version," "media version," and
"display version" without needing to do a PCI ID -> platform -> version
translation.

Although our current platforms don't yet expose these registers (and the
next couple we release probably won't have them yet either), the
hardware teams would still like to see us move to this independent
numbering scheme now in preparation.  For i915 that means we should try
to eliminate all usage of INTEL_GEN() throughout our code and instead
replace it with separate GRAPHICS_VER(), MEDIA_VER(), and DISPLAY_VER()
constructs in the code.  For old platforms, these will all usually give
the same value for each IP block (aside from a few special cases like
GLK which we can no more accurately represent as graphics=9 +
display=10), but future platforms will have more flexibility to bump IP
version numbers independently.

The upcoming ADL-P platform will have a display version of 13 and a
graphics version of 12, so let's just the first step of breaking out
DISPLAY_VER(), but leaving the rest of INTEL_GEN() untouched for now.
For now we'll automatically derive the display version from the
platform's INTEL_GEN() value except in cases where an alternative
display version is explicitly provided in the device info structure.

We also add some helper macros IS_DISPLAY_VER(i915, ver) and
IS_DISPLAY_RANGE(i915, from, until) that match the behavior of the
existing gen-based macros.  However unlike IS_GEN(), we will implement
those macros with direct comparisons rather than trying to maintain a
mask to help compiler optimization.  In practice the optimization winds
up not being used in very many places (since the vast majority of our
platform checks are of the form "gen >= x") so there is pretty minimal
size reduction in the final driver binary[1].  We're also likely going
to need to extend these version numbers to non-integer major.minor
values at some point in the future, so the mask approach won't work at
all once we get to platforms like that.

 [1] The results before/after the next patch in this series, which
     switches our code over to the new display macros:

        $ size i915.ko.{orig,new}
           text    data     bss     dec     hex filename
        2940291  102944    5384 3048619  2e84ab i915.ko.orig
        2940723  102956    5384 3049063  2e8667 i915.ko.new

v2:
 - Move version into device info's display sub-struct. (Jani)
 - Add extra parentheses to macros.  (Jani)
 - Note the lack of genmask optimization in the display-based macros and
   give size data.  (Lucas)

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: NMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: NLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210320044245.3920043-3-matthew.d.roper@intel.com
      01eb15c9
  11. 13 2月, 2021 1 次提交
    • M
      drm/i915: FPGA_DBG is display-specific · a321c3c6
      由 Matt Roper 提交于 
      Although the bspec's description doesn't make it very clear, the
hardware architects have confirmed that the FPGA_DBG register that we
use to check for unclaimed MMIO accesses is display-specific and will
only properly flag unclaimed MMIO transactions for registers in the
display range.  If a platform doesn't have display, FPGA_DBG itself will
not be available and should not be checked.  Let's move the feature flag
into intel_device_info.display to more accurately reflect this.

Given that we now know FPGA_DBG is display-specific, it could be argued
that we should only check it on out intel_de_*() functions.  However
let's not make that change right now; keeping the checks in all of the
existing locations still helps us catch cases where regular
intel_uncore_*() functions use bad MMIO offset math / base addresses and
accidentally wind up landing within an unused area within the display
MMIO range.  It will also help catch cases where userspace-initiated
MMIO (e.g., IGT's intel_reg tool) attempt to read bad offsets within the
display range.

v2:  Add missing hunk with the update to the HAS_FPGA_DBG_UNCLAIMED
     macro.  (CI)

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: NMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: NLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210212222049.3516344-1-matthew.d.roper@intel.com
      a321c3c6
  13. 21 1月, 2021 1 次提交
    • C
      drm/i915/adl_s: Add ADL-S platform info and PCI ids · 0883d63b
      由 Caz Yokoyama 提交于 
      - Add the initial platform information for Alderlake-S.
- Specify ppgtt_size value
- Add dma_mask_size
- Add ADLS REVIDs
- HW tracking(Selective Update Tracking Enable) has been
  removed from ADLS. Disable PSR2 till we enable software/
  manual tracking.

v2:
- Add support for different ADLS SOC steppings to select
  correct GT/DISP stepping based on Bspec 53655 based on
  feedback from Matt Roper.(aswarup)

v3:
- Make display/gt steppings info generic for reuse with TGL and ADLS.
- Modify the macros to reuse tgl_revids_get()
- Add HTI support to adls device info.(mdroper)

v4:
- Rebase on TGL patch for applying WAs based on stepping info from
  Matt Roper's feedback.(aswarup)

v5:
- Replace macros with PCI IDs in revid to stepping table.

v6: remove stray adls_revids (Lucas)

Bspec: 53597
Bspec: 53648
Bspec: 53655
Bspec: 48028
Bspec: 53650
BSpec: 50422

Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: NCaz Yokoyama <caz.yokoyama@intel.com>
Signed-off-by: NAditya Swarup <aditya.swarup@intel.com>
Reviewed-by: NLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: NLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210119192931.1116500-2-lucas.demarchi@intel.com
      0883d63b
  15. 09 1月, 2021 1 次提交
  17. 24 12月, 2020 1 次提交
  19. 14 10月, 2020 1 次提交
  21. 18 8月, 2020 1 次提交
  23. 14 7月, 2020 2 次提交
  25. 09 7月, 2020 4 次提交
  27. 10 6月, 2020 1 次提交
    • M
      drm/i915/rkl: RKL uses ABOX0 for pixel transfers · 62afef28
      由 Matt Roper 提交于 
      Rocket Lake uses the same 'abox0' mechanism to handle pixel data
transfers from memory that gen11 platforms used, rather than the
abox1/abox2 interfaces used by TGL/DG1.  For the most part this is a
hardware implementation detail that's transparent to driver software,
but we do have to program a couple of tuning registers (MBUS_ABOX_CTL
and BW_BUDDY registers) according to which ABOX instances are used by a
platform.  Let's track the platform's ABOX usage in the device info
structure and use that to determine which instances of these registers
to program.

As an exception to this rule is that even though TGL/DG1 use ABOX1+ABOX2
for data transfers, we're still directed to program the ABOX_CTL
register for ABOX0; so we'll handle that as a special case.

v2:
 - Store the mask of platform-specific abox registers in the device
   info structure.
 - Add a TLB_REQ_TIMER() helper macro.  (Aditya)

v3:
 - Squash ABOX and BW_BUDDY patches together and use a single mask for
   both of them, plus a special-case for programming the ABOX0 instance
   on all gen12.  (Ville)

Bspec: 50096
Bspec: 49218
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: NMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200606025740.3308880-2-matthew.d.roper@intel.comReviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      62afef28
  29. 05 6月, 2020 1 次提交
  31. 03 6月, 2020 1 次提交
  33. 20 5月, 2020 1 次提交
  35. 15 5月, 2020 1 次提交
  37. 18 4月, 2020 1 次提交
  39. 04 4月, 2020 1 次提交
  41. 19 2月, 2020 1 次提交
  43. 16 2月, 2020 1 次提交
  45. 06 2月, 2020 1 次提交
    • S
      drm/i915: Manipulate DBuf slices properly · 0f0f9aee
      由 Stanislav Lisovskiy 提交于 
      Start manipulating DBuf slices as a mask,
but not as a total number, as current approach
doesn't give us full control on all combinations
of slices, which we might need(like enabling S2
only can't enabled by setting enabled_slices=1).

Removed wrong code from intel_get_ddb_size as
it doesn't match to BSpec. For now still just
use DBuf slice until proper algorithm is implemented.

Other minor code refactoring to get prepared
for major DBuf assignment changes landed:
- As now enabled slices contain a mask
  we still need some value which should
  reflect how much DBuf slices are supported
  by the platform, now device info contains
  num_supported_dbuf_slices.
- Removed unneeded assertion as we are now
  manipulating slices in a more proper way.

v2: Start using enabled_slices in dev_priv

v3: "enabled_slices" is now "enabled_dbuf_slices_mask",
    as this now sits in dev_priv independently.

v4: - Fixed debug print formatting to hex(Matt Roper)
    - Optimized dbuf slice updates to be used only
      if slice union is different from current conf(Matt Roper)
    - Fixed some functions to be static(Matt Roper)
    - Created a parameterized version for DBUF_CTL to
      simplify DBuf programming cycle(Matt Roper)
    - Removed unrequred field from GEN10_FEATURES(Matt Roper)

v5: - Removed redundant programming dbuf slices helper(Ville Syrjälä)
    - Started to use parameterized loop for hw readout to get slices
      (Ville Syrjälä)
    - Added back assertion checking amount of DBUF slices enabled
      after DC states 5/6 transition, also added new assertion
      as starting from ICL DMC seems to restore the last DBuf
      power state set, rather than power up all dbuf slices
      as assertion was previously expecting(Ville Syrjälä)

v6: - Now using enum for DBuf slices in this patch (Ville Syrjälä)
    - Removed gen11_assert_dbuf_enabled and put gen9_assert_dbuf_enabled
      back, as we really need to have a single unified assert here
      however currently enabling always slice 1 is enforced by BSpec,
      so we will have to OR enabled slices mask with 1 in order
      to be consistent with BSpec, that way we can unify that
      assertion and against the actual state from the driver, but
      not some hardcoded value.(concluded with Ville)
    - Remove parameterized DBUF_CTL version, to extract it to another
      patch.(Ville Syrjälä)
v7:
    - Removed unneeded hardcoded return value for older gens from
      intel_enabled_dbuf_slices_mask - this now is handled in a
      unified manner since device info anyway returns max dbuf slices
      as 1 for older platforms(Matthew Roper)
    - Now using INTEL_INFO(dev_priv)->num_supported_dbuf_slices instead
      of intel_dbuf_max_slices function as it is trivial(Matthew Roper)

v8: - Fixed icl_dbuf_disable to disable all dbufs still(Ville Syrjälä)

v9: - Renamed _DBUF_CTL_S to DBUF_CTL_S(Ville Syrjälä)
    - Now using power_domain mutex to protect from race condition, which
      can occur because intel_dbuf_slices_update might be running in
      parallel to gen9_dc_off_power_well_enable being called from
      intel_dp_detect for instance, which causes assertion triggered by
      race condition, as gen9_assert_dbuf_enabled might preempt this
      when registers were already updated, while dev_priv was not.
Reviewed-by: NMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: NStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200202230630.8975-6-stanislav.lisovskiy@intel.com
      0f0f9aee
  47. 09 12月, 2019 1 次提交
  49. 30 10月, 2019 2 次提交
  51. 26 10月, 2019 1 次提交
  53. 18 10月, 2019 1 次提交
  55. 23 9月, 2019 1 次提交
  57. 12 9月, 2019 1 次提交
  59. 31 7月, 2019 1 次提交
  61. 25 7月, 2019 1 次提交