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  1. 22 4月, 2007 3 次提交
    • E
      [ARM] 4304/1: removes the unnecessary bit number from CKENnn_XXXX · 7053acbd
      由 Eric Miao 提交于 
      This patch removes the unnecessary bit number from CKENnn_XXXX
definitions for PXA, so that

	CKEN0_PWM0 --> CKEN_PWM0
	CKEN1_PWM1 --> CKEN_PWM1
	...
	CKEN24_CAMERA --> CKEN_CAMERA

The reasons for the change of these defitions are:

1. they do not scale - they are currently valid for pxa2xx, but
definitely not valid for pxa3xx, e.g., pxa3xx has bit 3 for camera
instead of bit 24

2. they are unnecessary - the peripheral name within the definition
has already announced its usage, we don't need those bit numbers
to know which peripheral we are going to enable/disable clock for

3. they are inconvenient - think about this: a driver programmer
for pxa has to remember which bit in the CKEN register to turn
on/off

Another change in the patch is to make the definitions equal to its
clock bit index, so that

   #define CKEN_CAMERA  (24)

instead of

   #define CKEN_CAMERA  (1 << 24)

this change, however, will add a run-time bit shift operation in
pxa_set_cken(), but the benefit of this change is that it scales
when bit index exceeds 32, e.g., pxa3xx has two registers CKENA
and CKENB, totally 64 bit for this, suppose CAMERA clock enabling
bit is CKENB:10, one can simply define CKEN_CAMERA to be (32 + 10)
and so that pxa_set_cken() need minimum change to adapt to that.
Signed-off-by: Neric miao <eric.y.miao@gmail.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      7053acbd
    • P
      [ARM] 4236/2: basic {enable,disable}_irq_wake() support for PXA · 4fe4a2bf
      由 Philipp Zabel 提交于 
      pxa_set_gpio_wake handles GPIOs > 1, so IRQ_TO_GPIO has to be used
instead of just substracting IRQ_GPIO0 from the irq number.
      4fe4a2bf
    • R
      [ARM] Remove needless linux/ptrace.h includes · 0f0a00be
      由 Russell King 提交于 
      Lots of places in arch/arm were needlessly including linux/ptrace.h,
resumably because we used to pass a struct pt_regs to interrupt
handlers.  Now that we don't, all these ptrace.h includes are
redundant.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      0f0a00be
  3. 08 3月, 2007 1 次提交
  5. 02 3月, 2007 1 次提交
  7. 27 2月, 2007 1 次提交
  9. 21 2月, 2007 1 次提交
  11. 17 2月, 2007 1 次提交
  13. 10 2月, 2007 1 次提交
  15. 08 2月, 2007 1 次提交
  17. 31 12月, 2006 2 次提交
  19. 13 12月, 2006 3 次提交
  21. 08 12月, 2006 1 次提交
  23. 06 12月, 2006 1 次提交
  25. 04 12月, 2006 1 次提交
    • L
      [ARM] 3881/4: xscale: clean up cp0/cp1 handling · afe4b25e
      由 Lennert Buytenhek 提交于 
      XScale cores either have a DSP coprocessor (which contains a single
40 bit accumulator register), or an iWMMXt coprocessor (which contains
eight 64 bit registers.)

Because of the small amount of state in the DSP coprocessor, access to
the DSP coprocessor (CP0) is always enabled, and DSP context switching
is done unconditionally on every task switch.  Access to the iWMMXt
coprocessor (CP0/CP1) is enabled only when an iWMMXt instruction is
first issued, and iWMMXt context switching is done lazily.

CONFIG_IWMMXT is supposed to mean 'the cpu we will be running on will
have iWMMXt support', but boards are supposed to select this config
symbol by hand, and at least one pxa27x board doesn't get this right,
so on that board, proc-xscale.S will incorrectly assume that we have a
DSP coprocessor, enable CP0 on boot, and we will then only save the
first iWMMXt register (wR0) on context switches, which is Bad.

This patch redefines CONFIG_IWMMXT as 'the cpu we will be running on
might have iWMMXt support, and we will enable iWMMXt context switching
if it does.'  This means that with this patch, running a CONFIG_IWMMXT=n
kernel on an iWMMXt-capable CPU will no longer potentially corrupt iWMMXt
state over context switches, and running a CONFIG_IWMMXT=y kernel on a
non-iWMMXt capable CPU will still do DSP context save/restore.

These changes should make iWMMXt work on PXA3xx, and as a side effect,
enable proper acc0 save/restore on non-iWMMXt capable xsc3 cores such
as IOP13xx and IXP23xx (which will not have CONFIG_CPU_XSCALE defined),
as well as setting and using HWCAP_IWMMXT properly.
Signed-off-by: NLennert Buytenhek <buytenh@wantstofly.org>
Acked-by: NDan Williams <dan.j.williams@intel.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      afe4b25e
  27. 30 11月, 2006 2 次提交
  29. 15 10月, 2006 1 次提交
  31. 09 10月, 2006 1 次提交
    • D
      IRQ: Use the new typedef for interrupt handler function pointers · 40220c1a
      由 David Howells 提交于 
      Use the new typedef for interrupt handler function pointers rather than
actually spelling out the full thing each time.  This was scripted with the
following small shell script:

#!/bin/sh
egrep -nHrl -e 'irqreturn_t[ 	]*[(][*]' $* |
while read i
do
    echo $i
    perl -pi -e 's/irqreturn_t\s*[(]\s*[*]\s*([_a-zA-Z0-9]*)\s*[)]\s*[(]\s*int\s*,\s*void\s*[*]\s*[)]/irq_handler_t \1/g' $i || exit $?
done
Signed-Off-By: NDavid Howells <dhowells@redhat.com>
      40220c1a
  33. 07 10月, 2006 1 次提交
  35. 04 10月, 2006 2 次提交
  37. 02 10月, 2006 1 次提交
  39. 28 9月, 2006 1 次提交
    • D
      USB: pxa2xx_udc understands GPIO based VBUS sensing · b2bbb20b
      由 David Brownell 提交于 
      This updates the PXA 25x UDC board-independent infrastructure for VBUS sensing
and the D+ pullup.  The original code evolved from rather bizarre support on
Intel's "Lubbock" reference hardware, so that on more sensible hardware it
doesn't work as well as it could/should.

The change is just to teach the UDC driver how to use built-in PXA GPIO pins
directly.  This reduces the amount of board-specfic object code needed, and
enables the use of a VBUS sensing IRQ on boards (like Gumstix) that have one.
With VBUS sensing, the UDC is unclocked until a host is actually connected.
Signed-off-by: NDavid Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
      b2bbb20b
  41. 27 8月, 2006 1 次提交
  43. 02 8月, 2006 1 次提交
  45. 03 7月, 2006 1 次提交
  47. 02 7月, 2006 1 次提交
  49. 01 7月, 2006 1 次提交
  51. 29 6月, 2006 3 次提交
  53. 25 6月, 2006 1 次提交
  55. 21 6月, 2006 1 次提交
  57. 20 6月, 2006 3 次提交