The address bits from MC4_STATUS differ only between K8 and the rest so
no need for a per-family method.

No functional change.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Use the struct mce directly instead of copying from it into a custom
struct err_regs.

No functionality change.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

The only difference is that F10h used to sport ganged DCTs and F15h
doesn't so adjust the F10h routine and reuse it.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Remove unused defines, drop family names from define names.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Remove reporting of errors with UC bit set - this is done by the MCE
decoding code anyway and this driver deals with DRAM ECC errors only. UC
(NB uncorrectable error) doesn't necessarily mean it is a DRAM error.
Remove unused macros while at it.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

The fact whether we are chipkill capable or not does not have any
bearing when computing the channel index on a ganged DCT configuration
so remove that. Also, simplify debug statements. Finally, remove old
error injection leftovers, while at it.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Remove family names from macro names, drop single bit defines and
comment their meaning instead.

No functional change.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Shorten macro names, remove family name from macros, fix macro
arguments, shorten debug strings.

No functionality change.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

* Restrict DCT ganged mode check since only Fam10h supports it
* Adjust DRAM type detection for BD since it only supports DDR3
* Remove second and thus unneeded DCLR read in k8_early_channel_count() - we do
  that in read_mc_regs()
* Cleanup comments and remove family names from register macros
* Remove unused defines

There should be no functional change resulting from this patch.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Do not read DBAM regs twice and simplify code around them.

There should be no functional change resulting from this patch.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Replace hard to read hex constants with a continuous masks macro.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

This function maps the system address to the normalized DCT address.
Document what the code does for more clarity and wrap insane bitmasks in
a more understandable macro which generates them. Also, reduce number of
arguments passed to the function. Finally, rename this function to what
it actually does.

No functional change.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Cleanup and simplify f10_determine_channel(); make it more readable.
Also drop f10_map_intlv_en_to_shift() in favor of simply counting the
bits in F1x124[DramIntlvEn] which is equivalent.

There should be no functionality change resulting from this patch.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Add a struct representing the DRAM chip select base/limit register
pairs. Concentrate all CS handling in a single function. Also, add CS
looping macros for cleaner, more readable code. While at it, adjust code
to F15h. Finally, do smaller macro names cleanups (remove family names
from register macros) and debug messages clarification.

No functional change.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Adjust to F15h, simplify code, fixup macros.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Add a struct representing the DRAM base/limit range pairs and remove all
cached subfields. Replace them with accessor functions, which actually
saves us some space:

   text    data     bss     dec     hex filename
  14712    1577     336   16625    40f1 drivers/edac/amd64_edac_mod.o.after
  14831    1609     336   16776    4188 drivers/edac/amd64_edac_mod.o.before

Also, it simplifies the code a lot allowing to merge the K8 and F10h
routines.

No functional change.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

F15h "multiplexes" between the configuration space of the two DRAM
controllers by toggling D18F1x10C[DctCfgSel] while F10h has a different
set of registers for DCT0, and DCT1 in extended PCI config space.

Add DCT configuration space accessors per family thus wrapping all the
different access prerequisites. Clean up code while at it, shorten
names.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Raise the debug level of these routines so that their output get issued
out only when the highest debug level is selected. Otherwise, don't
pollute driver debug output.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

amd64_debug_display_dimm_sizes() reports the distribution of the DIMMs
on each DRAM controller and its chip select sizes. Thus, the last don't
have anything to do with whether we're running in ganged DCT mode or not
- their sizes don't change all of a sudden. Fix that by removing the
ganged-check and dump DCT0's config for DCT1 when in ganged mode since
they're identical.
Reported-and-tested-by: NMarkus Trippelsdorf <markus@trippelsdorf.de>
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Minor formatting fixup since the information which core was associated
with the MCE is not always valid.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Building for X86_32 produces shift count warnings, so use BIT_64() to
eliminate the warnings.

drivers/edac/mce_amd.c:778: warning: left shift count >= width of type
drivers/edac/mce_amd.c:778: warning: left shift count >= width of type
Signed-off-by: NRandy Dunlap <randy.dunlap@oracle.com>
Cc: Doug Thompson <dougthompson@xmission.com>
Cc: bluesmoke-devel@lists.sourceforge.net
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Now that everything is inplace, enable MCE decoding on F15h. Make
initcall routine a bit more readable.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

F15h adds a sixth MCE bank: adjust bank number check in the injection
code.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Shorten up MCi_STATUS flags and add BD's new deferred and poison types.
Also, simplify formatting.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Make macro names shorter thus making code shorter and more clear.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Add decoder for FP MCEs.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Integrate the single FIROB signature into an expanded table along with
the new BD MCE types.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

by (almost) reusing the F10h one since the signatures are the same.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

F15h BD doesn't generate LS MCEs so warn about it.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

MCE bank 2 is redefined from a BU to a CU (Combined Unit) bank on F15h.
Add a decoder function for CU MCEs.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Add support for decoding F15h IC MCEs.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Add a decoder for F15h DC MCEs to support the new types of DC MCEs
introduced by the BD microarchitecture.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

F15h enlarges the extended error code of an MCE to a 5-bit field
(MCi_STATUS[20:16]). Add a mask variable which default 0xf is overridden
on F15h.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

K8 does not allow for an atomic RMW to a cacheline as F10h does so
disable the error injection interface for it.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Make the ->{get|set}_sdram_scrub_rate return the actual scrub rate
bandwidth it succeeded setting and remove superfluous arg pointer used
for that. A negative value returned still means that an error occurred
while setting the scrubrate. Document this for future reference.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Now that all prerequisites are in place, drop the two-stage driver
instances initialization in favor of the following simple init sequence:

1. Probe PCI device: we only test ECC capabilities here and if none exit
early.

2. If the hw supports ECC and it is/can be enabled, we init the per-node
instance.

Remove "amd64_" prefix from static functions touched, while at it.

There actually should be no visible functional change resulting from
this patch.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

Rework the code to check the hardware ECC capabilities at PCI probing
time. We do all further initialization only if we actually can/have ECC
enabled.

While at it:
0. Fix function naming.
1. Simplify/clarify debug output.
2. Remove amd64_ prefix from the static functions
3. Reorganize code.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

This is in preparation for the init path reorganization where we want
only to

1) test whether a particular node supports ECC
2) can it be enabled

and only then do the necessary allocation/initialization. For that,
we need to decouple the ECC settings of the node from the instance's
descriptor.

The should be no functional change introduced by this patch.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

PCI ECS is being enabled by default since 2.6.26 on AMD so this code is
just superfluous now, remove it.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>

AMD_NB pulls in the dependency on PCI. Clarify/fix help text while at it.
Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>