- 30 5月, 2014 3 次提交
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由 Alexandre Belloni 提交于
This is a driver for the complex divider cells found on Marvell Berlin2 SoCs. The cells come in two flavors: single register cells and shared register cells. Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Alexandre Belloni 提交于
This is a clock driver for the simple PLLs found on Berlin SoCs. With repect to PLL registers and features, BG2/BG2CD and BG2Q are slightly different, e.g. different allowed VCO dividers and bit shifts. Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sebastian Hesselbarth 提交于
This is a driver for the AVPLLs built upon a VCO with 8 channels each found on Marvell Berlin2 SoCs. While both VCOs found on BG2/BG2CD share the same register set, sometimes registers shifts for one of the VCOs are a bit off. Nothing serious that should require a separate driver, so deal with both VCOs in a single driver instead. Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 29 5月, 2014 1 次提交
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由 Stephen Boyd 提交于
Failure to terminate this match table can lead to boot failures depending on where the compiler places the match table. Cc: Gabriel FERNANDEZ <gabriel.fernandez@st.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 28 5月, 2014 4 次提交
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由 Sachin Kamat 提交于
Fixes the following warning: WARNING: drivers/built-in.o(.text.unlikely+0x2c50): Section mismatch in reference from the function exynos4_clk_sleep_init() to the (unknown reference) .init.data:(unknown) The function exynos4_clk_sleep_init() references the (unknown reference) __initdata (unknown). This is often because exynos4_clk_sleep_init lacks a __initdata annotation or the annotation of (unknown) is wrong. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Reported-by: Nkbuild test robot <fengguang.wu@intel.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Tomasz Figa 提交于
Commit c686078 ("clk: divider: Add round to closest divider") introduced a helper function to check whether given divisor is the best one instead of direct check. However due to int type used instead of unsigned long for passing calculated rates to this function in certain cases an overflow could occur, for example when trying to obtain maximum possible clock rate by calling clk_round_rate(..., UINT_MAX). This patch fixes this issue by changing the type of rate, now and best arguments of the function to unsigned long, which is the type that should be used for clock rates. Signed-off-by: NTomasz Figa <t.figa@samsung.com> Acked-by: NMaxime Coquelin <maxime.coquelin@st.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Stephen Boyd 提交于
Failure to terminate this match table can lead to boot failures depending on where the compiler places the match table. Signed-off-by: NStephen Boyd <sboyd@codeaurora.org> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Alex Elder 提交于
Implement the clk->determine_rate method for Broadcom Kona peripheral clocks. This allows a peripheral clock to be re-parented in order to satisfy a rate change request. This takes the place of the previous kona_peri_clk_round_rate() functionality, though that function remains because it is used by the new one. The parent clock that allows the peripheral clock to produce a rate closest to the one requested is the one selected, though the current parent is used by default. Signed-off-by: NAlex Elder <elder@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 24 5月, 2014 9 次提交
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由 Georgi Djakov 提交于
The address of the blsp2_ahb_clk register is incorrect. Fix it. Signed-off-by: NGeorgi Djakov <gdjakov@mm-sol.com> Reviewed-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Krzysztof Kozlowski 提交于
This patch adds support for S2MPS14 PMIC clocks (BT and AP) to the s2mps11 clock driver. Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Acked-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Krzysztof Kozlowski 提交于
There is no need for checking if 'clk_table' is not NULL twice (first after allocation and second at the end of probe()). Also move allocation of this 'clk_table' to probe from s2mps11_clk_parse_dt as this is logical place for it. Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Krzysztof Kozlowski 提交于
Add of_clk_del_provider to remove previously registered clock provider. Add of_node_put to decrement the ref count of clock nodes. Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Valentin Ilie 提交于
When it fails to allocate div, gate should be free'd before return Signed-off-by: NValentin Ilie <valentin.ilie@gmail.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Maxime COQUELIN 提交于
Commit 1d9fe6b97 ("clk: divider: Fix best div calculation for power-of-two and table dividers") introduces a regression in its _table_round_up function. When the divider passed to this function is greater than the max divider available in the table, this function returns table's max divider. Problem is that it causes an infinite loop in clk_divider_bestdiv() because _next_div() will never return a value greater than maxdiv. Instead of returning table's max divider, this patch returns INT_MAX. Reported-by: NFabio Estevam <festevam@gmail.com> Reported-by: NShawn Guo <shawn.guo@freescale.com> Tested-by: NFabio Estevam <festevam@gmail.com> Tested-by: NShawn Guo <shawn.guo@freescale.com> Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Geert Uytterhoeven 提交于
- Limit ruler to 80 characters (was: 81), - Widen rate column by 1 for nicer spacing, - Right-align numbers and their column headers, - Move a newline to reduce the number of seq_printf() calls, - Use set_puts() for fixed strings. Before: clock enable_cnt prepare_cnt rate accuracy --------------------------------------------------------------------------------- extal 2 2 20000000 0 thermal 1 1 20000000 0 cp 0 0 10000000 0 tpu0 0 0 10000000 0 tmu0 0 0 10000000 0 main 1 1 20000000 0 pll3 0 0 1600000000 0 ddr 0 0 200000000 0 zb3d2 0 0 200000000 0 zb3 0 0 400000000 0 pll1 4 4 1560000000 0 oscclk 0 0 126953 0 rclk 1 1 31738 0 cmt1 0 0 31738 0 cmt0 1 1 31738 0 imp 0 0 390000000 0 After: clock enable_cnt prepare_cnt rate accuracy -------------------------------------------------------------------------------- extal 2 2 20000000 0 thermal 1 1 20000000 0 cp 0 0 10000000 0 tpu0 0 0 10000000 0 tmu0 0 0 10000000 0 main 1 1 20000000 0 pll3 0 0 1600000000 0 ddr 0 0 200000000 0 zb3d2 0 0 200000000 0 zb3 0 0 400000000 0 pll1 4 4 1560000000 0 oscclk 0 0 126953 0 rclk 1 1 31738 0 cmt1 0 0 31738 0 cmt0 1 1 31738 0 imp 0 0 390000000 0 Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Heiko Stuebner 提交于
From: Heiko Stuebner <heiko@sntech.de> Similar to muxes which already have a read-only flag there sometimes exist dividers which should not be changed by the clock framework but whose value still should be readable. Therefore add a READ_ONLY flag similar to the mux-one to clk-divider Signed-off-by: NHeiko Stuebner <heiko@sntech.de> [changed flag bit to BIT(5) as suggested by Tomasz Figa] Signed-off-by: NThomas Abraham <thomas.ab@samsung.com> Acked-by: NTomasz Figa <t.figa@samsung.com> Acked-by: NMax Schwarz <max.schwarz@online.de> Tested-by: NMax Schwarz <max.schwarz@online.de> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Ulrich Hecht 提交于
Driver for the R8A7740's clocks that are too specific to be supported by a generic driver. Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: NGeert Uytterhoeven <geert@linux-m68k.org> Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 23 5月, 2014 7 次提交
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由 Andrew Bresticker 提交于
Initialize the XUSB-related clocks with appropriate parents and rates for both Tegra114 and Tegra124. Signed-off-by: NJim Lin <jilin@nvidia.com> Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Andrew Bresticker 提交于
Currently the Tegra1x4 clock init code hard-codes the mux setting for xusb_hs_src and treats it as a fixed-factor clock. It is, however, a mux which can be parented by either xusb_ss_src/2 or pll_u_60M. Add the fixed-factor clock xusb_ss_div2 and put an entry in periph_clks[] for the xusb_hs_src mux. Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Jim Lin 提交于
The parent-to-index mapping for xusb_fs_src is incorrect. Fix it by adding a mux table. Signed-off-by: NJim Lin <jilin@nvidia.com> Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Jim Lin 提交于
Enable hardware control of PLLE spread-spectrum, IDDQ, and enable controls when enabling PLLE. The hardware (e.g. XUSB) using PLLE will use these controls for power-saving optimizations. Signed-off-by: NJim Lin <jilin@nvidia.com> Signed-off-by: NAndrew Bresticker <abrestic@chromium.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Anders Berg 提交于
Add clk driver to support clock blocks found on the AXM55xx devices. The driver provides clock implementations for three different types of clock devices on the AXM55xx device: PLL clock, a clock divider and a clock mux. Signed-off-by: NAnders Berg <anders.berg@lsi.com> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Laurent Pinchart 提交于
The MSTP[SC]R registers have clock stop bits, not clock enable bits. The bit value should thus be inverted in the is_enabled() operation. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sylwester Nawrocki 提交于
This patch adds of_clk_get_by_clkspec() helper function, which does only a struct clk lookup from the clock providers. It is used in the subsequent patch where parsing of a clock from device tree and the lookup from providers needed to be split. Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 22 5月, 2014 1 次提交
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由 Linus Walleij 提交于
The IM-PD1 PrimeCells all have pclk assignments though this clock cannot be controlled, and we need to provide this as a dummy clock for the PL061 GPIO driver to probe, so let's assign it to all the cells on the board. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 20 5月, 2014 1 次提交
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由 Michal Simek 提交于
Just fix missing ">" in the email. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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- 17 5月, 2014 2 次提交
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由 Stephen Boyd 提交于
When consolidating the msm8660 GCC probe code I forgot to keep around these temporary clock registrations. Put them back so the clock tree is not entirely orphaned. Fixes: 49fc825f (clk: qcom: Consolidate common probe code) Signed-off-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Tuomas Tynkkynen 提交于
The value written to PLLE_AUX was incorrect due to a wrong variable being used. Without this fix SATA does not work. Cc: stable@vger.kernel.org Signed-off-by: NTuomas Tynkkynen <ttynkkynen@nvidia.com> Tested-by: NMikko Perttunen <mperttunen@nvidia.com> Reviewed-by: NThierry Reding <treding@nvidia.com> Tested-by: NThierry Reding <treding@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org> [mturquette@linaro.org: improved changelog]
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- 15 5月, 2014 2 次提交
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由 Arnd Bergmann 提交于
The impd1 code on mach-integrator can be a loadable module, so we have to export icst_clk_register, integrator_impd1_clk_init and integrator_impd1_clk_exit. Signed-off-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Hans de Goede 提交于
__clk_get_hw is supposed to be used by clk providers, not clk consumers. Signed-off-by: NHans de Goede <hdegoede@redhat.com> Reviewed-by: NUlf Hansson <ulf.hansson@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 13 5月, 2014 3 次提交
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由 Simon Horman 提交于
The R8A7779 SoC has several clocks that are too custom to be supported in a generic driver. Those clocks are all fixed rate clocks with multiplier and divisor set according to boot mode configuration. Based on work for R-Car Gen2 SoCs by Laurent Pinchart. Cc: devicetree@vger.kernel.org Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Ben Dooks 提交于
With the addition of clock-indices, we need to change the renesas clock implementation to use these instead of the local definition of "renesas,clock-indices". Since this will break booting with older device trees, we add a simple auto-detection of which properties are present. Signed-off-by: NBen Dooks <ben.dooks@codethink.co.uk> Acked-by: NGeert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Dinh Nguyen 提交于
The C0(mpu_clk), C1(main_clk), and C2(dbg_base_clk) outputs from the main PLL go through a pre-divider before coming into the system. These registers were hidden for the CycloneV platform, but are now used for the ArriaV platform. This patch updates the clock driver to read the div-reg property for the socfpga-periph-clk clocks. Also moves the div_mask define to clk.h for re-use. Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
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- 12 5月, 2014 3 次提交
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由 Zhangfei Gao 提交于
Signed-off-by: NHaifeng Yan <haifeng.yan@linaro.org> Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org>
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由 Zhangfei Gao 提交于
Add hisi_clk_register_gate register clk gate table Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org>
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由 Zhangfei Gao 提交于
Platform hix5hd2 use mux table, so use clk_register_mux_table instead Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org>
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- 06 5月, 2014 2 次提交
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由 Emilio López 提交于
HdG: add header exporting clk_sunxi_mmc_phase_control Signed-off-by: NEmilio López <emilio@elopez.com.ar> Signed-off-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Emilio López 提交于
This commit implements .determine_rate, so that our factor clocks can be reparented when needed. Signed-off-by: NEmilio López <emilio@elopez.com.ar> Signed-off-by: NHans de Goede <hdegoede@redhat.com> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 04 5月, 2014 1 次提交
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由 Catalin Marinas 提交于
Following arm64 commit bc3ee18a (arm64: init: Move of_clk_init to time_init()), vexpress_osc_of_setup() is called via of_clk_init() long before initcalls are issued. Initialising the vexpress oscillators requires the vespress sysregs to be already initialised, so this patch adds an explicit call to vexpress_sysreg_of_early_init() in vexpress oscillator setup function. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Tested-by: NWill Deacon <will.deacon@arm.com> Acked-by: NWill Deacon <will.deacon@arm.com> Tested-by: NPawel Moll <pawel.moll@arm.com> Acked-by: NPawel Moll <pawel.moll@arm.com> Cc: Mike Turquette <mturquette@linaro.org>
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- 01 5月, 2014 1 次提交
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由 Kumar Gala 提交于
* Remove CE2_SLEEP_CLK, doesn't exist on 8960 family SoCs * Fix incorrect offset for PMIC_SSBI2_RESET * Fix typo: SIC_TIC -> SPS_TIC_H SFAB_ADM0_M2_A_CLK -> SFAB_ADM0_M2_H_CLK * Fix naming convention: SFAB_CFPB_S_HCLK -> SFAB_CFPB_S_H_CLK SATA_SRC_CLK -> SATA_CLK_SRC Signed-off-by: NKumar Gala <galak@codeaurora.org> Reviewed-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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