Instead of the 'amdgpu_ring_priority_level' type,
the 'amdgpu_gfx_pipe_priority' type was used,
which is an error when setting ring priority.
This is a minor error, but may cause problems in the future.

Instead of AMDGPU_RING_PRIO_2 = 2, we can use AMDGPU_RING_PRIO_MAX = 3,
but AMDGPU_RING_PRIO_2 = 2 is used for compatibility with
AMDGPU_GFX_PIPE_PRIO_HIGH = 2, and not change the behavior of the
code.
Signed-off-by: NGrigory Vasilyev <h0tc0d3@gmail.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

cayman_default_state and cayman_default_size are only
used in ni.c.  Single file symbols should be static.
So move their definitions to cayman_blit_shaders.h
and change their storage-class-specifier to static.

Remove unneeded cayman_blit_shader.c

cayman_ps/vs definitions were removed with
commit 4f862967 ("drm/radeon/kms: remove r6xx+ blit copy routines")
So their declarations in cayman_blit_shader.h
are not needed, so remove them.
Signed-off-by: NTom Rix <trix@redhat.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

The data revision was not changed to 5 from 4 when the CG flags
were extended to 64-bits.  Since this was missed I took
the opportunity to add future upper 64-bits of PG flags
as well so we don't need to bump it again when that comes.
Signed-off-by: NTom St Denis <tom.stdenis@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Add CONFIG_X86 check to fix the build error.

Fixes: 49aa98ca ("drm/amd/amdgpu: Only reserve vram for firmware with vega9 MS_HYPERV host.")
Reported-by: Nkernel test robot <lkp@intel.com>
Signed-off-by: NYongqiang Sun <yongqiang.sun@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Application could change XNACK enabled to disabled while KFD is draining
stale retry fault, therefore the check for whether to drain retry faults
must be before the check for whether xnack_enabled, to avoid report
incorrect vm fault after application changes XNACK mode.
Signed-off-by: NPhilip Yang <Philip.Yang@amd.com>
Reviewed-by: NFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Use flexible array member in ip discovery struct as recommended[1].

[1] https://www.kernel.org/doc/html/latest/process/deprecated.html#zero-length-and-one-element-arrays

v2: squash in struct_size fixes
Signed-off-by: NLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

With this, we can support more CG flags.
Signed-off-by: NEvan Quan <evan.quan@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

driver loading failed on VEGA10 SRIOV VF with linux host due to a wide
range of stolen reserved vram.
Since VEGA10 SRIOV VF need to reserve vram for firmware with windows
Hyper_V host specifically, check hypervisor type to only reserve
memory for it, and the range of the reserved vram can be limited
to between 5M-7M area.

Fixes: faad5cca ("drm/amdgpu: Add stolen reserved memory for MI25 SRIOV.")
Signed-off-by: NYongqiang Sun <yongqiang.sun@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Check that adev->gfx.ras is valid before using it.

Fixes: 6475ae2b ("drm/amdgpu: add UTCL2 RAS poison query for Aldebaran (v2)")
CC: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: NFelix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: NMukul Joshi <mukul.joshi@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Smatch reports this issue
hdcp1_execution.c:500:29: warning: function
  'mod_hdcp_hdcp1_dp_execution' with external linkage
  has definition

The storage-class-specifier extern is not needed in a
definition, so remove it.
Reviewed-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NTom Rix <trix@redhat.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Enabling gfxoff quirk results in perfectly usable graphical user
interface on MacBook Pro (15-inch, 2019) with Radeon Pro Vega 20 4 GB.

Without the quirk, X server is completely unusable as every few seconds
there is gpu reset due to ring gfx timeout.
Signed-off-by: NTomasz Moń <desowin@gmail.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

DP/HDMI audio on AMD PRO VII stops working after S3:
[  149.450391] amdgpu 0000:63:00.0: amdgpu: MODE1 reset
[  149.450395] amdgpu 0000:63:00.0: amdgpu: GPU mode1 reset
[  149.450494] amdgpu 0000:63:00.0: amdgpu: GPU psp mode1 reset
[  149.983693] snd_hda_intel 0000:63:00.1: refused to change power state from D0 to D3hot
[  150.003439] amdgpu 0000:63:00.0: refused to change power state from D0 to D3hot
...
[  155.432975] snd_hda_intel 0000:63:00.1: CORB reset timeout#2, CORBRP = 65535

The offending commit is daf8de08 ("drm/amdgpu: always reset the asic in
suspend (v2)"). Commit 34452ac3 ("drm/amdgpu: don't use BACO for
reset in S3 ") doesn't help, so the issue is something different.

Assuming that to make HDA resume to D0 fully realized, it needs to be
successfully put to D3 first. And this guesswork proves working, by
moving amdgpu_asic_reset() to noirq callback, so it's called after HDA
function is in D3.

Fixes: daf8de08 ("drm/amdgpu: always reset the asic in suspend (v2)")
Signed-off-by: NKai-Heng Feng <kai.heng.feng@canonical.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Drop the trailing vcn.

Fixes: afc2f276 ("drm/amdgpu/vcn: add vcn support for vcn 3.1.2")
Reviewed-by: NJames Zhu <James.Zhu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

"Pre-multiplied" is the default pixel blend mode for KMS/DRM, as
documented in supported_modes of drm_plane_create_blend_mode_property():
https://cgit.freedesktop.org/drm/drm-misc/tree/drivers/gpu/drm/drm_blend.c

In this mode, both 'pixel alpha' and 'plane alpha' participate in the
calculation, as described by the pixel blend mode formula in KMS/DRM
documentation:

out.rgb = plane_alpha * fg.rgb +
          (1 - (plane_alpha * fg.alpha)) * bg.rgb

Considering the blend config mechanisms we have in the driver so far,
the alpha mode that better fits this blend mode is the
_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN, where the value for global_gain
is the plane alpha (global_alpha).

With this change, alpha property stops to be ignored. It also addresses
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1734

v2:
 * keep the 8-bit value for global_alpha_value (Nicholas)
 * correct the logical ordering for combined global gain (Nicholas)
 * apply to dcn10 too (Nicholas)
Signed-off-by: NMelissa Wen <mwen@igalia.com>
Tested-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Reviewed-by: NHarry Wentland <harry.wentland@amd.com>
Tested-by: NSimon Ser <contact@emersion.fr>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Use rcu_read_lock to read p->event_idr concurrently with other readers
and writers. Use p->event_mutex only for creating and destroying events
and in kfd_wait_on_events.

Protect the contents of the kfd_event structure with a per-event
spinlock that can be taken inside the rcu_read_lock critical section.

This eliminates contention of p->event_mutex in set_event, which tends
to be on the critical path for dispatch latency even when busy waiting
is used. It also eliminates lock contention in event interrupt handlers.
Since the p->event_mutex is now used much less, the impact of requiring
it in kfd_wait_on_events should also be much smaller.

This should improve event handling latency for processes using multiple
GPUs concurrently.

v2: Reschedule the worker periodically to avoid soft lockup warnings
Signed-off-by: NFelix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Sean Keely <Sean.Keely@amd.com> # v1
Tested-by: NSanjay Tripathi <sanjay.tripathi@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

'dm_services.h' included in 'freesync,c' is duplicated, so remove one.
Reported-by: NZeal Robot <zealci@zte.com.cn>
Signed-off-by: NLv Ruyi <lv.ruyi@zte.com.cn>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

SMU takes clock limits in Mhz units.  socclk and fclk were
using 10 khz units in some cases.  Switch to Mhz units.
Fixes higher than required SoC clocks.

Fixes: 97cf3299 ("drm/amd/pm: Removed fixed clock in auto mode DPM")
Reviewed-by: NPaul Menzel <pmenzel@molgen.mpg.de>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
Make dcn315 base its clock table off dcfclk rather than fclk.

This change also adds some sanity checking to make sure an
empty pmfw table does not result in invalid dal clocks.
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: NDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Variable igp_lane_info always is 0. 0 & any value = 0 and false.
In this way, all сonditional statements will false.

The code was leftover from when the code was ported from radeon
where igp_lane_info was derived from the vbios on supported
platforms.

[update commit message - Alex]
Signed-off-by: NGrigory Vasilyev <h0tc0d3@gmail.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Smatch reports these issues
si_blit_shaders.c:31:11: warning: symbol 'si_default_state'
  was not declared. Should it be static?
si_blit_shaders.c:253:11: warning: symbol 'si_default_size'
  was not declared. Should it be static?

Both symbols are only used in si.c.  Single file symbols
should be static.  So move the definition of
si_default_state and si_default_size to si_blit_shader.h
and change their storage-class-specifier to static.

Remove unneeded si_blit_shader.c
Reviewed-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NTom Rix <trix@redhat.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Fixes crash on MST Hub disconnect.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1849
Fixes: ee2698cf ("drm/amd/display: Changed pipe split policy to allow for multi-display pipe split")
Signed-off-by: NBenjamin Marty <info@benjaminmarty.ch>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Replace `if (!ret)` with `else` for simplification.
Signed-off-by: NGuo Zhengkui <guozhengkui@vivo.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

bo_adev is NULL for system memory mapping to GPU.

Fixes: 30671b44 ("drm/amdgpu: fix TLB flushing during eviction")
Signed-off-by: NPhilip Yang <Philip.Yang@amd.com>
Reviewed-by: NFelix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

- Add options to allow for configurable PHY options during PSR active
state
- Remove unused versioning and git hash
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: NAnthony Koo <Anthony.Koo@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
Function to calculate scaling ratios can be called with invalid plane
src/dest, causing a divide by zero.

[HOW]
Fail building scaling params if plane state src/dest rects are
unpopulated
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: NMichael Strauss <michael.strauss@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
The dp_trace structure is self contained component designed for
all dp trace, and the edp link trace should be a part of it;
Suggested-by: NWenjing Liu <wenjing.liu@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: NWenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: NCharlene Liu <Charlene.Liu@amd.com>
Acked-by: NTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: NLeo (Hanghong) Ma <hanghong.ma@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

- [FW Promotion] Release 0.0.111.0
- Check for invalid input params when building scaling params
- Move link_trace for edp to dp_trace
- Fix missing-prototypes warning
- Enable 3 plane for DCN 3.0 and 3.02
- Extract set stream attribute into link_hwss
- Revert Power down hardware if timer not trigger
- Add support for handling 128b/132b link training test request
- Add configuration options for AUX wake work around
- Remove underflow IRQ type
- Add flip interval workaround for low FPS in some game
- Remove assert for odm transition case
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Acked-by: NTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
No declaration of hubp1_wait_pipe_read_start found in header file.

[How]
Add its declaration.
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: NBecle Lee <becle.lee@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY&HOW]
Increase num of bottom planes to 2. Note that DCN 3.03 is left out
since it has max 2 planes.
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: NKrunoslav Kovac <Krunoslav.Kovac@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
Extract set stream attribute into link_hwss as part of the link hwss
refactor work.
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: NGeorge Shen <George.Shen@amd.com>
Acked-by: NTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: NWenjing Liu <wenjing.liu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: NGeorge Shen <George.Shen@amd.com>
Acked-by: NTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: NMartin Leung <Martin.Leung@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
DP2.x added new enum values for UHBR link rates in link training test
request for test automation. We need to add UHBR link rates test request
support in preparation for compliance test automation.

[how]
added a function that translate test link rate to dc link rate.  Call
the translation function to decide the requested test link rate.
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: NGeorge Shen <George.Shen@amd.com>
Acked-by: NTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: NWenjing Liu <wenjing.liu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Work around to try to wake unresponsive DP sinks may need to be adjusted
for certain sinks.

[How]
Add options to disable work around or adjust time spent trying to wake
unresponsive DPRX.
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: NMartin Leung <Martin.Leung@amd.com>
Acked-by: NTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: NJimmy Kizito <Jimmy.Kizito@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
Feature using the underflow IRQ type reverted

[HOW]
Removed underflow IRQ type entry
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: NMartin Leung <Martin.Leung@amd.com>
Acked-by: NTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: NAngus Wang <Angus.Wang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[WHY]
Some games experience low FPS issues when FreeSync is on and VSync is
toggled to half refresh rate.

[HOW]
First create a function to determine workaround conditions, which is
when we detect 2 or more VSync interrupts between flips and a very short
VSync to flip interval. We do the workaround during VSync interrupts and
set the v_total_max and min to nominal. We also cleanup after we exit
the game.
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com>
Reviewed-by: NAric Cyr <Aric.Cyr@amd.com>
Acked-by: NTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: NAngus Wang <Angus.Wang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Remove assert that will hit during odm transition case,
since this is a valid case.
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: NAlvin Lee <alvin.lee2@amd.com>
Acked-by: NTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: NEric Bernstein <eric.bernstein@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

For VG20 + XGMI bridge, all mappings PTEs cache in TC, this may have
stall invalid PTEs in TC because one cache line has 8 pages. Need always
flush_tlb after updating mapping.
Signed-off-by: NPhilip Yang <Philip.Yang@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Seems to cause a reboots or hangs on some systems.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1924
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1953
Fixes: daf8de08 ("drm/amdgpu: always reset the asic in suspend (v2)")
Reviewed-by: NLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

report by coccicheck:
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c:1951:2-3: Unneeded semicolon

Fixes: c543dcbe ("drm/amdgpu/vcn: Add VCN ras error query support")
Signed-off-by: NHaowen Bai <baihaowen@meizu.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Fix the kernel test robot warning below:

drivers/gpu/drm/amd/amdgpu/../display/dmub/inc/dmub_cmd.h:2893:12:
warning: variable 'temp' set but not used [-Wunused-but-set-variable]

Replaced the assignment to the unused temp variable with READ_ONCE()
macro to flush the writes. READ_ONCE() helps avoid the use of
volatile and makes it obvious from the code that the read here is
intentional. Also verified on x86 that the generated code is exactly the
same as before.
Reported-by: Nkernel test robot <lkp@intel.com>
Signed-off-by: NAashish Sharma <shraash@google.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>