1. 24 9月, 2007 1 次提交
    • J
      IB/mlx4: Fix data corruption triggered by wrong headroom marking order · 6e694ea3
      Jack Morgenstein 提交于
      This is an addendum to commit 0e6e7416 ("IB/mlx4: Handle new FW
      requirement for send request prefetching").  We also need to handle
      prefetch marking properly for S/G segments, or else the HCA may end up
      processing S/G segments that are not fully written and end up sending
      the wrong data.  This can actually cause data corruption in practice,
      especially on systems with relatively slow CPUs (where the HCA is more
      likely to prefetch while the CPU is in the middle of writing a work
      request into memory).
      
      We write S/G segments in reverse order into the WQE, in order to
      guarantee that the first dword of all cachelines containing S/G
      segments is written last (overwriting the headroom invalidation
      pattern).  The entire cacheline will thus contain valid data when the
      invalidation pattern is overwritten.
      Signed-off-by: NJack Morgenstein <jackm@dev.mellanox.co.il>
      Signed-off-by: NRoland Dreier <rolandd@cisco.com>
      6e694ea3
  2. 01 9月, 2007 12 次提交
  3. 31 8月, 2007 27 次提交