Add 2 SPI nodes to SOCFPGA device tree.
Signed-off-by: NThor Thayer <tthayer@opensource.altera.com>
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>

Add a 64KB ocram node for SOCFPGA.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>

Since the Synopsys GPIO IP can support multiple ports of varying widths, it
would make more sense to have the GPIO node DTS entry as this:

gpio0: gpio@ff708000{
	porta{
	};
};

Also, this is documented in the snps-dwapb-gpio.txt.
Suggested-by: NDoug Anderson <dianders@chromium.org>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>

Add the Altera SDRAM EDAC bindings and device tree changes to the Altera SoC
project.

There was a discussion thread on whether this driver should be an mfd driver
or just make use of syscon, which is already a mfd. Ultimately, the
decision to use a simple syscon interface was reached.[1]

[1] https://lkml.org/lkml/2014/7/30/514Signed-off-by: NThor Thayer <tthayer@opensource.altera.com>
Acked-by: NPavel Machek <pavel@denx.de>
[dinguyen] cleaned-up commit header and remove version history.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>

This patch adds socfpga Ethernet filter attributes for multicast
and unicast filters per Synopsys Ethernet IP configuration chosen
by Altera for the Cyclone 5 and Arria SOC FPGAs.
Signed-off-by: NVince Bridgers <vbridgers2013@gmail.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

add #reset-cells to socfpga.dtsi. This was missing from the
latest updates and caused the socfpga reset controller to fail
to load like so:

ffd05000.rstmgr: /soc/rstmgr@ffd05000 missing #reset-cells property
probe of ffd05000.rstmgr failed with error -22
Signed-off-by: NVince Bridgers <vbridgers2013@gmail.com>
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The SoCFPGA has two watchdog timers. Add them to the dtsi.
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
[dinh: modified patch to have correct irq flag]
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>

The cycloneV has three gpio controllers, each one with 29 gpios. This patch
adds the three controller with the gpio driver which is now sitting the
gpio tree.

Cc: devicetree@vger.kernel.org
Acked-by: NAlan Tull <atull@altera.com>
Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>

The mpu_clk, main_clk, and dbg_base_clk outputs from the main PLL go through a
pre-divider. Update socfpga.dtsi to represent those dividers for these
clocks.

Re-use the "div-reg" property that was used for the socfpga-gate-clock as this
is the same thing. Also update the documentation.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>

Add the necessary #reset-cells property to the rst-mgr node and
provide a header-file with all possible resets specified.
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>

Update all the SOCFPGA DTS files with USB entries.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>

The timers and uart can get their clock frequencies using the common clock
driver.
Reviewed-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>

Convert all socfpga DT files to the dtc preprocessor include syntax.
This allows to include header files in the devicetrees like other
SoC-types already do.
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>

Add both can controllers to the dtsi.
Reviewed-by: NPavel Machek <pavel@denx.de>
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>

Add all 4 i2c busses.
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>

Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>

The first interrupt is not at 180 but 104. Fix it.
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>

This patch adds the dts bindings documenation for the Altera SOCFPGA glue
layer for the Synopsys STMMAC ethernet driver.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This reverts commit 7e0b4cd0.

The binding changes need to be done differently as well, let's
take them through netdev, and merge the dts changes in a new
patch here.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This reverts commit d9c3f5df, which
should not have been merged via mmc-next.  It's in arm-soc instead now.

commit[7e0b4cd0 dts: socfpga: Add DTS entry for adding the stmmac glue
layer for stmmac.] references the sysmgr through its phandle. This patch
adds the appropriate sysmgr node for the gmac to use.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>

Introduce "altr,socfpga-dw-mshc" to enable Altera's SOCFPGA platform
specific implementation of the dw_mmc driver.

Also add the "syscon" binding to the "altr,sys-mgr" node. The clock
driver can use the syscon driver to toggle the register for the SD/MMC
clock phase shift settings.

Finally, fix an indentation error for the sysmgr node.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Acked-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Tested-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NChris Ball <chris@printf.net>

The periph_pll and sdram_pll can have multiple parents. Update the device tree
to list all the possible parents for the PLLs. Add an entry for the the
f2s_sdram_ref_clk, which is a possible parent for the sdram_pll.

Also remove the clock-frequency entry in the f2s_periph_ref_clk, as this
property should be placed in dts file.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de>

This patch adds the dts bindings documenation for the Altera SOCFPGA glue
layer for the Synopsys STMMAC ethernet driver.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Acked-by: NDavid S. Miller <davem@davemloft.net>
---
v3: Remove stray empty line at end of socfpga_cyclone5_socdk.dts
v2: Use the dwmac-sti as an example for a glue layer and split patch up
to have dts as a separate patch. Also cc dts maintainers since there is
a new binding.

Introduce "altr,socfpga-dw-mshc" to enable Altera's SOCFPGA platform
specific implementation of the dw_mmc driver.

Also add the "syscon" binding to the "altr,sys-mgr" node. The clock
driver can use the syscon driver to toggle the register for the SD/MMC
clock phase shift settings.

Finally, fix an indentation error for the sysmgr node.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Acked-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Tested-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NChris Ball <chris@printf.net>

The clk-phase property is used to represent the 2 clock phase values that is
needed for the SD/MMC driver. Add a prepare function to the clk_ops, that will
use the syscon driver to set sdmmc_clk's phase shift that is located in the
system manager.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Acked-by: NZhangfei Gao <zhangfei.gao@linaro.org>
Acked-by: NJaehoon Chung <jh80.chung@samsung.com>
---
v9: none
v8: Use degrees in the clk-phase binding property
v7: Add dts property to represent the clk phase of the sdmmc_clk. Add a
    prepare function to the gate clk that will toggle clock phase setting.
    Remove the "altr,socfpga-sdmmc-sdr-clk" clock type.
v6: Add a new clock type "altr,socfpga-sdmmc-sdr-clk" that will be used to
    set the phase shift settings.
v5: Use the "snps,dw-mshc" binding
v4: Use the sdmmc_clk prepare function to set the phase shift settings
v3: Not use the syscon driver because as of 3.13-rc1, the syscon driver is
    loaded after the clock driver.
v2: Use the syscon driver

The pl330 dmac won't be added to the list of amba devices, as it doesn't have
a clock entry.
Add the clock.
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>

Sets the appropriate L2-cache latencies for the SOCFPGA platform.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>

Some of the clocks that were designated gate-clk do not have a gate, so
change those clocks to be of periph-clk type.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The s2f_* clocks are called h2f_* in the datasheets.
Rename them accordingly in the socfpga.dtsi.
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>

Some of the clock nodes and the rst-/sysmgr use wrong indentation.
Fix it.
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>

Assign a clock for the twd-timer.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Acked-by: NRob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ian.campbell@citrix.com>
CC: linux-arm-kernel@lists.infradead.org

"dw-apb-timer-osc" and "dw-apb-timer-sp" are the same implementation of the
DW APB timer, just fed by different clocks. Thus, deprecate both
"dw-apb-timer-osc" and "dw-apb-timer-sp" in lieu of "dw-apb-timer".
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Reviewed-by: NPavel Machek <pavel@denx.de>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
CC: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ian.campbell@citrix.com>
CC: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
CC: Jamie Iles <jamie@jamieiles.com>
Cc: John Stultz <john.stultz@linaro.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: NOlof Johansson <olof@lixom.net>

v3:
- Split out a separate that cleans up the timer entries and clock information.
- Clearly states which binding is deprecated in the bindings doc.

v2:
- Deprecate the "dw-apb-timer-osc" and "dw-apb-timer-sp" but maintain
  backwards compatibility in the driver.

Add bindings for "socfpga-gate-clk" clocks. These clocks directly feed
the peripherals.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Reviewed-by: NPavel Machek <pavel@denx.de>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Olof Johansson <olof@lixom.net>
Cc: Pavel Machek <pavel@denx.de>
CC: <linux@arm.linux.org.uk>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Add entry for 2nd GMAC controller. Add the correct clocks for the GMAC.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Reviewed-by: NPavel Machek <pavel@denx.de>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Olof Johansson <olof@lixom.net>
Cc: Pavel Machek <pavel@denx.de>
CC: <linux@arm.linux.org.uk>

v2:
- Moved "disabled" status to dtsi file
Signed-off-by: NOlof Johansson <olof@lixom.net>

Adds the main PLL clock groups for SOCFPGA into device tree file
so that the clock framework to query the clock and clock rates
appropriately.

$cat /sys/kernel/debug/clk/clk_summary
   clock                        enable_cnt  prepare_cnt  rate
---------------------------------------------------------------------
 osc1                           2           2            25000000
    sdram_pll                   0           0            400000000
       s2f_usr2_clk             0           0            66666666
       ddr_dq_clk               0           0            200000000
       ddr_2x_dqs_clk           0           0            400000000
       ddr_dqs_clk              0           0            200000000
    periph_pll                  2           2            500000000
       s2f_usr1_clk             0           0            50000000
       per_base_clk             4           4            100000000
       per_nand_mmc_clk         0           0            25000000
       per_qsi_clk              0           0            250000000
       emac1_clk                1           1            125000000
       emac0_clk                0           0            125000000
    main_pll                    1           1            1600000000
       cfg_s2f_usr0_clk         0           0            100000000
       main_nand_sdmmc_clk      0           0            100000000
       main_qspi_clk            0           0            400000000
       dbg_base_clk             0           0            400000000
       mainclk                  0           0            400000000
       mpuclk                   1           1            800000000
          smp_twd               1           1            200000000
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Reviewed-by: NPavel Machek <pavel@denx.de>
Signed-off-by: NOlof Johansson <olof@lixom.net>

This patch adds #dma-cells property to PL330 DMA controller nodes for
supporting generic dma dt bindings on SOCFPGA platform. #dma-channels
and #dma-requests are not required now but added in advance.
Signed-off-by: NPadmavathi Venna <padma.v@samsung.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Up to this point, support for socfpga has only been on a virtual
platform. Now that actual hardware is available, we add the appropriate
device tree source files.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Tested-by: NPavel Machek <pavel@denx.de>
Reviewed-by: NPavel Machek <pavel@denx.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Olof Johansson <olof@lixom.net>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Enable SMP for the SOCFPGA platform.
Signed-off-by: NPavel Machek <pavel@denx.de>
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Reviewed-by: NRob Herring <rob.herring@calxeda.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Adding core definitions for Altera's SOCFPGA ARM platform.
Mininum support for Altera's SOCFPGA Cyclone 5 hardware.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Reviewed-by: NPavel Machek <pavel@denx.de>
Reviewed-by: NRob Herring <rob.herring@calxeda.com>
Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>