- 05 11月, 2014 1 次提交
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由 Murali Karicheri 提交于
K2E SoC has a second PCI port based on Synopsis Designware PCIe h/w. Add DT bindings to support PCI controller for port 1 for this SoC. Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com> Signed-off-by: NSantosh Shilimkar <ssantosh@kernel.org>
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- 01 10月, 2014 2 次提交
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由 Grygorii Strashko 提交于
The K2E MDIO io space has different start address. Hence, fix it to be 0x24200f00 according to TRM. Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
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由 Grygorii Strashko 提交于
Keystone supports dma-coherent on USB master and also needs dma-ranges to specify the hardware alias memory range in which DMA can be operational. Such configuration applied for USB0 devices, but It's missed for USB1 device which is present only in K2E SoC - hence apply it. Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
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- 23 9月, 2014 1 次提交
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由 Grygorii Strashko 提交于
Add Keystone 2 DSP GPIO nodes for SoCs: k2hk: DSP GPIO banks 0-7 correspond to DSP0-DSP7 k2l: DSP GPIO banks 0-3 correspond to DSP0-DSP3 k2e: DSP GPIO bank 0 corresponds to DSP0 Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
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- 26 2月, 2014 1 次提交
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由 Murali Karicheri 提交于
Keystone2 Edison (K2E) is a Quad Cortex A15 based SoC with 1 DSP. It has standard peripherals such as i2c, spi, uart, timer, pcie, etc similar to k2hk, but without wireless hardwares. This patch add support for k2 Edison SoC and EVM. This re-uses the common keystone.dtsi to include common bindings across the various k2 devices. Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com> Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
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