- 05 1月, 2015 3 次提交
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由 Joerg Roedel 提交于
This code only runs when action == BUS_NOTIFY_REMOVED_DEVICE, so it can't be BUS_NOTIFY_DEL_DEVICE. Signed-off-by: NJoerg Roedel <jroedel@suse.de>
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由 Joerg Roedel 提交于
Since commit 1196c2fb a domain is only destroyed in the notifier path if it is hot-unplugged. This caused a domain leakage in iommu_attach_device when a driver was unbound from the device and bound to VFIO. In this case the device is attached to a new domain and unlinked from the old domain. At this point nothing points to the old domain anymore and its memory is leaked. Fix this by explicitly freeing the old domain in iommu_attach_domain. Fixes: 1196c2fb (iommu/vt-d: Fix dmar_domain leak in iommu_attach_device) Cc: stable@vger.kernel.org # v3.18 Tested-by: NJerry Hoemann <jerry.hoemann@hp.com> Signed-off-by: NJoerg Roedel <jroedel@suse.de>
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由 Laurent Pinchart 提交于
Commit a720b41c ("iommu/arm-smmu: change IOMMU_EXEC to IOMMU_NOEXEC") has inverted and replaced the IOMMU_EXEC flag with IOMMU_NOEXEC. Update the driver accordingly. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: NJoerg Roedel <jroedel@suse.de>
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- 17 12月, 2014 1 次提交
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由 Mark Brown 提交于
The Exynos IOMMU driver uses the ARM specific dmac_flush_range() and outer_flush_range() functions. This breaks the build on arm64 allmodconfig in -next since support has been merged for some Exynos ARMv8 SoCs. Add a dependency on ARM to keep things building until either the driver has the ARM dependencies removed or the ARMv8 architecture code implements these ARM specific APIs. Signed-off-by: NMark Brown <broonie@kernel.org> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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- 16 12月, 2014 3 次提交
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由 Jiang Liu 提交于
Use helpers to access irq_cfg data structure associated with IRQ, instead of accessing irq_data->chip_data directly. Later we can rewrite those helpers to support hierarchy irqdomain. Signed-off-by: NJiang Liu <jiang.liu@linux.intel.com> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: iommu@lists.linux-foundation.org Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Joerg Roedel <joro@8bytes.org> Link: http://lkml.kernel.org/r/1414397531-28254-20-git-send-email-jiang.liu@linux.intel.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
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由 Jiang Liu 提交于
Use helpers to access irq_cfg data structure associated with IRQ, instead of accessing irq_data->chip_data directly. Later we can rewrite those helpers to support hierarchy irqdomain. Signed-off-by: NJiang Liu <jiang.liu@linux.intel.com> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: iommu@lists.linux-foundation.org Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Joerg Roedel <joro@8bytes.org> Link: http://lkml.kernel.org/r/1414397531-28254-19-git-send-email-jiang.liu@linux.intel.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
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由 Jiang Liu 提交于
Use helpers to access irq_cfg data structure associated with IRQ, instead of accessing irq_data->chip_data directly. Later we can rewrite those helpers to support hierarchy irqdomain. Signed-off-by: NJiang Liu <jiang.liu@linux.intel.com> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: iommu@lists.linux-foundation.org Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Joerg Roedel <joro@8bytes.org> Link: http://lkml.kernel.org/r/1414397531-28254-18-git-send-email-jiang.liu@linux.intel.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
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- 14 12月, 2014 1 次提交
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由 Jesse Barnes 提交于
This could be useful for debug in the future if we want to track major/minor faults more closely, and also avoids the put_page trick we used with gup. In order to do this, we also track the task struct in the PASID state structure. This lets us update the appropriate task stats after the fault has been handled, and may aid with debug in the future as well. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Tested-by: NOded Gabbay <oded.gabbay@amd.com> Cc: Joerg Roedel <jroedel@suse.de> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 05 12月, 2014 1 次提交
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由 Robin Murphy 提交于
Since the data pointer in the DT node is public and may be overwritten by conflicting code, move the DT-probed IOMMU ops to a private list where they will be safe. Acked-by: NGrant Likely <grant.likely@linaro.org> Signed-off-by: NRobin Murphy <robin.murphy@arm.com> [will: added missing #include and missing ')'] Signed-off-by: NWill Deacon <will.deacon@arm.com>
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- 04 12月, 2014 1 次提交
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由 Thierry Reding 提交于
The memory controller on NVIDIA Tegra exposes various knobs that can be used to tune the behaviour of the clients attached to it. Currently this driver sets up the latency allowance registers to the HW defaults. Eventually an API should be exported by this driver (via a custom API or a generic subsystem) to allow clients to register latency requirements. This driver also registers an IOMMU (SMMU) that's implemented by the memory controller. It is supported on Tegra30, Tegra114 and Tegra124 currently. Tegra20 has a GART instead. The Tegra SMMU operates on memory clients and SWGROUPs. A memory client is a unidirectional, special-purpose DMA master. A SWGROUP represents a set of memory clients that form a logical functional unit corresponding to a single device. Typically a device has two clients: one client for read transactions and one client for write transactions, but there are also devices that have only read clients, but many of them (such as the display controllers). Because there is no 1:1 relationship between memory clients and devices the driver keeps a table of memory clients and the SWGROUPs that they belong to per SoC. Note that this is an exception and due to the fact that the SMMU is tightly integrated with the rest of the Tegra SoC. The use of these tables is discouraged in drivers for generic IOMMU devices such as the ARM SMMU because the same IOMMU could be used in any number of SoCs and keeping such tables for each SoC would not scale. Acked-by: NJoerg Roedel <jroedel@suse.de> Signed-off-by: NThierry Reding <treding@nvidia.com>
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- 02 12月, 2014 5 次提交
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由 Robin Murphy 提交于
If the IOMMU supports pages smaller than the CPU page size, segments which lie at offsets within the CPU page may be mapped based on the finer-grained IOMMU page boundaries. This minimises the amount of non-buffer memory between the CPU page boundary and the start of the segment which must be mapped and therefore exposed to the device, and brings the default iommu_map_sg implementation in line with iommu_map/unmap with respect to alignment. Signed-off-by: NRobin Murphy <robin.murphy@arm.com> Signed-off-by: NJoerg Roedel <jroedel@suse.de>
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由 Jiang Liu 提交于
There's an off-by-one bug in function __domain_mapping(), which may trigger the BUG_ON(nr_pages < lvl_pages) when (nr_pages + 1) & superpage_mask == 0 The issue was introduced by commit 9051aa02 "intel-iommu: Combine domain_pfn_mapping() and domain_sg_mapping()", which sets sg_res to "nr_pages + 1" to avoid some of the 'sg_res==0' code paths. It's safe to remove extra "+1" because sg_res is only used to calculate page size now. Reported-And-Tested-by: NSudeep Dutt <sudeep.dutt@intel.com> Signed-off-by: NJiang Liu <jiang.liu@linux.intel.com> Cc: <stable@vger.kernel.org> # >= 3.0 Acked-By: NDavid Woodhouse <David.Woodhouse@intel.com> Signed-off-by: NJoerg Roedel <jroedel@suse.de>
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由 Marek Szyprowski 提交于
IOMMU drivers can be initialized from of_iommu helpers. Such drivers don't need to provide device_add callbacks to operate properly, so there is no need to fail initialization if the callback is missing. Acked-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: NWill Deacon <will.deacon@arm.com>
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由 Will Deacon 提交于
The generic IOMMU device-tree bindings can be used to add arbitrary OF masters to an IOMMU with a compliant binding. This patch introduces of_iommu_configure, which does exactly that. Acked-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NJoerg Roedel <jroedel@suse.de> Acked-by: NMarek Szyprowski <m.szyprowski@samsung.com> Tested-by: NRobin Murphy <robin.murphy@arm.com> Signed-off-by: NWill Deacon <will.deacon@arm.com>
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由 Will Deacon 提交于
IOMMU drivers must be initialised before any of their upstream devices, otherwise the relevant iommu_ops won't be configured for the bus in question. To solve this, a number of IOMMU drivers use initcalls to initialise the driver before anything has a chance to be probed. Whilst this solves the immediate problem, it leaves the job of probing the IOMMU completely separate from the iommu_ops to configure the IOMMU, which are called on a per-bus basis and require the driver to figure out exactly which instance of the IOMMU is being requested. In particular, the add_device callback simply passes a struct device to the driver, which then has to parse firmware tables or probe buses to identify the relevant IOMMU instance. This patch takes the first step in addressing this problem by adding an early initialisation pass for IOMMU drivers, giving them the ability to store some per-instance data in their iommu_ops structure and store that in their of_node. This can later be used when parsing OF masters to identify the IOMMU instance in question. Acked-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NJoerg Roedel <jroedel@suse.de> Acked-by: NMarek Szyprowski <m.szyprowski@samsung.com> Tested-by: NRobin Murphy <robin.murphy@arm.com> Signed-off-by: NWill Deacon <will.deacon@arm.com>
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- 23 11月, 2014 1 次提交
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由 Jiang Liu 提交于
Simplify PCI MSI code by initializing msi_desc.nvec_used and msi_desc.msi_attrib.multiple when creating MSI descriptors. Also remove redundant checks in IRQ remapping drivers, PCI MSI core already guarantees these. Signed-off-by: NJiang Liu <jiang.liu@linux.intel.com> Acked-by: NBjorn Helgaas <bhelgaas@google.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Yingjoe Chen <yingjoe.chen@mediatek.com> Cc: Yijing Wang <wangyijing@huawei.com> Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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- 18 11月, 2014 7 次提交
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由 Jiang Liu 提交于
Implement required callback functions for intel-iommu driver to support DMAR unit hotplug. Signed-off-by: NJiang Liu <jiang.liu@linux.intel.com> Reviewed-by: NYijing Wang <wangyijing@huawei.com> Signed-off-by: NJoerg Roedel <jroedel@suse.de>
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由 Jiang Liu 提交于
Enhance error recovery in function intel_enable_irq_remapping() by tearing down all created data structures. Signed-off-by: NJiang Liu <jiang.liu@linux.intel.com> Reviewed-by: NYijing Wang <wangyijing@huawei.com> Signed-off-by: NJoerg Roedel <jroedel@suse.de>
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由 Jiang Liu 提交于
Implement required callback functions for intel_irq_remapping driver to support DMAR unit hotplug. Signed-off-by: NJiang Liu <jiang.liu@linux.intel.com> Signed-off-by: NJoerg Roedel <jroedel@suse.de>
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由 Jiang Liu 提交于
According to Intel VT-d specification, _DSM method to support DMAR hotplug should exist directly under corresponding ACPI object representing PCI host bridge. But some BIOSes doesn't conform to this, so search for _DSM method in the subtree starting from the ACPI object representing the PCI host bridge. Signed-off-by: NJiang Liu <jiang.liu@linux.intel.com> Reviewed-by: NYijing Wang <wangyijing@huawei.com> Signed-off-by: NJoerg Roedel <jroedel@suse.de>
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由 Jiang Liu 提交于
On Intel platforms, an IO Hub (PCI/PCIe host bridge) may contain DMAR units, so we need to support DMAR hotplug when supporting PCI host bridge hotplug on Intel platforms. According to Section 8.8 "Remapping Hardware Unit Hot Plug" in "Intel Virtualization Technology for Directed IO Architecture Specification Rev 2.2", ACPI BIOS should implement ACPI _DSM method under the ACPI object for the PCI host bridge to support DMAR hotplug. This patch introduces interfaces to parse ACPI _DSM method for DMAR unit hotplug. It also implements state machines for DMAR unit hot-addition and hot-removal. The PCI host bridge hotplug driver should call dmar_hotplug_hotplug() before scanning PCI devices connected for hot-addition and after destroying all PCI devices for hot-removal. Signed-off-by: NJiang Liu <jiang.liu@linux.intel.com> Reviewed-by: NYijing Wang <wangyijing@huawei.com> Signed-off-by: NJoerg Roedel <jroedel@suse.de>
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由 Jiang Liu 提交于
Introduce functions to support dynamic IOMMU seq_id allocating and releasing, which will be used to support DMAR hotplug. Also rename IOMMU_UNITS_SUPPORTED as DMAR_UNITS_SUPPORTED. Signed-off-by: NJiang Liu <jiang.liu@linux.intel.com> Reviewed-by: NYijing Wang <wangyijing@huawei.com> Signed-off-by: NJoerg Roedel <jroedel@suse.de>
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由 Jiang Liu 提交于
Introduce helper function dmar_walk_resources to walk resource entries in DMAR table and ACPI buffer object returned by ACPI _DSM method for IOMMU hot-plug. Signed-off-by: NJiang Liu <jiang.liu@linux.intel.com> Signed-off-by: NJoerg Roedel <jroedel@suse.de>
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- 14 11月, 2014 5 次提交
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由 Will Deacon 提交于
When domains are set with the DOMAIN_ATTR_NESTING flag, we must ensure that we allocate them to stage-2 context banks if the hardware permits it. This patch adds support for the attribute to the ARM SMMU driver, with the actual stage being determined depending on the features supported by the hardware. Signed-off-by: NWill Deacon <will.deacon@arm.com>
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由 Thierry Reding 提交于
Currently the driver registers IOMMU bus operations for all busses even if no ARM SMMU is present on a system. Depending on the driver probing order this prevents the driver for the real IOMMU to register itself as the bus-wide IOMMU. Signed-off-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NWill Deacon <will.deacon@arm.com>
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由 Will Deacon 提交于
Some versions of GCC get unduly upset when confronted with a switch that doesn't explicitly handle all cases of an enum, despite having an implicit default case following the actualy switch statement: drivers/iommu/amd_iommu.c: In function 'amd_iommu_capable': >> drivers/iommu/amd_iommu.c:3409:2: warning: enumeration value 'IOMMU_CAP_NOEXEC' not handled in switch [-Wswitch] switch (cap) { This patch adds a case for IOMMU_CAP_NOEXEC to the amd IOMMU driver to remove this warning. Cc: Joerg Roedel <jroedel@suse.de> Signed-off-by: NWill Deacon <will.deacon@arm.com>
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由 Antonios Motakis 提交于
The ARM SMMU supports the IOMMU_NOEXEC protection flag. Add the corresponding IOMMU capability. Signed-off-by: NAntonios Motakis <a.motakis@virtualopensystems.com> Signed-off-by: NWill Deacon <will.deacon@arm.com>
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由 Antonios Motakis 提交于
Exposing the XN flag of the SMMU driver as IOMMU_NOEXEC instead of IOMMU_EXEC makes it enforceable, since for IOMMUs that don't support the XN flag pages will always be executable. Signed-off-by: NAntonios Motakis <a.motakis@virtualopensystems.com> Acked-by: NJoerg Roedel <jroedel@suse.de> Signed-off-by: NWill Deacon <will.deacon@arm.com>
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- 12 11月, 2014 1 次提交
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由 Oded Gabbay 提交于
This patch fixes a bug in the accounting of the device_state. In the current code, the device_state was put (decremented) too many times, which sometimes lead to the driver getting stuck permanently in put_device_state_wait(). That happen because the device_state->count would go below zero, which is never supposed to happen. The root cause is that the device_state was decremented in put_pasid_state() and put_pasid_state_wait() but also in all the functions that call those functions. Therefore, the device_state was decremented twice in each of these code paths. The fix is to decouple the device_state accounting from the pasid_state accounting - remove the call to put_device_state() from the put_pasid_state() and the put_pasid_state_wait()) Signed-off-by: NOded Gabbay <oded.gabbay@amd.com> Signed-off-by: NJoerg Roedel <jroedel@suse.de>
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- 06 11月, 2014 1 次提交
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由 Li, Zhen-Hua 提交于
The function context_set_address_root() and set_root_value are setting new address in a wrong way, and this patch is trying to fix this problem. According to Intel Vt-d specs(Feb 2011, Revision 1.3), Chapter 9.1 and 9.2, field ctp in root entry is using bits 12:63, field asr in context entry is using bits 12:63. To set these fields, the following functions are used: static inline void context_set_address_root(struct context_entry *context, unsigned long value); and static inline void set_root_value(struct root_entry *root, unsigned long value) But they are using an invalid method to set these fields, in current code, only a '|' operator is used to set it. This will not set the asr to the expected value if it has an old value. For example: Before calling this function, context->lo = 0x3456789012111; value = 0x123456789abcef12; After we call context_set_address_root(context, value), expected result is context->lo == 0x123456789abce111; But the actual result is: context->lo == 0x1237577f9bbde111; So we need to clear bits 12:63 before setting the new value, this will fix this problem. Signed-off-by: NLi, Zhen-Hua <zhen-hual@hp.com> Signed-off-by: NJoerg Roedel <jroedel@suse.de>
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- 05 11月, 2014 1 次提交
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由 Joerg Roedel 提交于
Add optional CONFIG_COMPILE_TEST to dependency list. Signed-off-by: NJoerg Roedel <jroedel@suse.de>
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- 04 11月, 2014 7 次提交
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由 Axel Lin 提交于
Signed-off-by: NAxel Lin <axel.lin@ingics.com> Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: NJoerg Roedel <jroedel@suse.de>
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由 Kiran Padwal 提交于
Use the wrapper function for retrieving the platform data instead of accessing dev->platform_data directly. Signed-off-by: NKiran Padwal <kiran.padwal@smartplayin.com> Signed-off-by: NJoerg Roedel <jroedel@suse.de>
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由 Kiran Padwal 提交于
Use the wrapper function for retrieving the platform data instead of accessing dev->platform_data directly. Signed-off-by: NKiran Padwal <kiran.padwal@smartplayin.com> Signed-off-by: NJoerg Roedel <jroedel@suse.de>
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由 Heiko Stübner 提交于
When some part of bus_set_iommu fails it should undo any made changes and not simply leave everything as is. This includes unregistering the bus notifier in iommu_bus_init when add_iommu_group fails and also setting the bus->iommu_ops back to NULL. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NJoerg Roedel <jroedel@suse.de>
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由 Joerg Roedel 提交于
The IOMMU-API works on page boundarys, unlike the DMA-API which can work with sub-page buffers. The sg->offset field does not make sense on the IOMMU level, so force it to be 0. Do some error-path consolidation while at it. Signed-off-by: NJoerg Roedel <jroedel@suse.de>
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由 Olav Haugan 提交于
Mapping and unmapping are more often than not in the critical path. map_sg allows IOMMU driver implementations to optimize the process of mapping buffers into the IOMMU page tables. Instead of mapping a buffer one page at a time and requiring potentially expensive TLB operations for each page, this function allows the driver to map all pages in one go and defer TLB maintenance until after all pages have been mapped. Additionally, the mapping operation would be faster in general since clients does not have to keep calling map API over and over again for each physically contiguous chunk of memory that needs to be mapped to a virtually contiguous region. Signed-off-by: NOlav Haugan <ohaugan@codeaurora.org> Signed-off-by: NJoerg Roedel <jroedel@suse.de>
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由 Daniel Kurtz 提交于
The rk3288 has several iommus. Each iommu belongs to a single master device. There is one device (ISP) that has two slave iommus, but that case is not yet supported by this driver. At subsys init, the iommu driver registers itself as the iommu driver for the platform bus. The master devices find their slave iommus using the "iommus" field in their devicetree description. Since each slave iommu belongs to exactly one master, their is no additional data needed at probe to associate a slave with its master. An iommu device's power domain, clock and irq are all shared with its master device, and the master device must be careful to attach from the iommu only after powering and clocking it (and leave it powered and clocked before detaching). Because their is no guarantee what the status of the iommu is at probe, and since the driver does not even know if the device is powered, we delay requesting its irq until the master device attaches, at which point we have a guarantee that the device is powered and clocked and we can reset it and disable its interrupt mask. An iommu_domain describes a virtual iova address space. Each iommu_domain has a corresponding page table that lists the mappings from iova to physical address. For the rk3288 iommu, the page table has two levels: The Level 1 "directory_table" has 1024 4-byte dte entries. Each dte points to a level 2 "page_table". Each level 2 page_table has 1024 4-byte pte entries. Each pte points to a 4 KiB page of memory. An iommu_domain is created when a dma_iommu_mapping is created via arm_iommu_create_mapping. Master devices can then attach themselves to this mapping (or attach the mapping to themselves?) by calling arm_iommu_attach_device(). This in turn instructs the iommu driver to write the page table's physical address into the slave iommu's "Directory Table Entry" (DTE) register. In fact multiple master devices, each with their own slave iommu device, can all attach to the same mapping. The iommus for these devices will share the same iommu_domain and therefore point to the same page table. Thus, the iommu domain maintains a list of iommu devices which are attached. This driver relies on the iommu core to ensure that all devices have detached before destroying a domain. v6: - add .add/remove_device() callbacks. - parse platform_device device tree nodes for "iommus" property - store platform device pointer as group iommudata - Check for existence of iommu group instead of relying on a dev_get_drvdata() to return NULL for a NULL device. v7: - fixup some strings. - In rk_iommu_disable_paging() # and % were reversed. Signed-off-by: NDaniel Kurtz <djkurtz@chromium.org> Signed-off-by: NSimon Xue <xxm@rock-chips.com> Reviewed-by: NGrant Grundler <grundler@chromium.org> Reviewed-by: NStéphane Marchesin <marcheu@chromium.org> Tested-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NJoerg Roedel <jroedel@suse.de>
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- 23 10月, 2014 2 次提交
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由 SF Markus Elfring 提交于
A semantic patch approach was proposed with the subject "[PATCH with Coccinelle?] Deletion of unnecessary checks before specific function calls" on 2014-03-05. https://lkml.org/lkml/2014/3/5/344 http://article.gmane.org/gmane.comp.version-control.coccinelle/3513/ This patch pattern application was repeated with the help of the software "Coccinelle 1.0.0-rc22" on the source files for Linux 3.17.1. An extract of the automatically generated update suggestions is shown here. It was determined that the affected source code places call functions which perform input parameter validation already. It is therefore not needed that a similar safety check is repeated at the call site. Signed-off-by: NMarkus Elfring <elfring@users.sourceforge.net> Signed-off-by: NJoerg Roedel <jroedel@suse.de>
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由 Suman Anna 提交于
The debugfs entry 'pagetable' that shows the page table entry (PTE) data currently outputs only data that can be fit into a page. Switch the entry to use the seq_file interface so that it can show all the valid page table entries. The patch also corrected the output for L2 entries, and prints the proper L2 PTE instead of the previous L1 page descriptor pointer. Signed-off-by: NSuman Anna <s-anna@ti.com> Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: NJoerg Roedel <jroedel@suse.de>
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