- 08 10月, 2010 3 次提交
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由 Haojian Zhuang 提交于
Signed-off-by: NHaojian Zhuang <haojian.zhuang@marvell.com> Acked-by: NAntonio Ospite <ospite@studenti.unina.it> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
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由 Igor Grinberg 提交于
Signed-off-by: NIgor Grinberg <grinberg@compulab.co.il> Signed-off-by: NMike Rapoport <mike@compulab.co.il> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
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由 Igor Grinberg 提交于
USB2.0 Device Controller (U2DC) which is found in Marvell PXA3xx. U2DC supports both High and Full speed modes. PXA320 and PXA300 U2DC supports only UTMI interface. PXA310 U2DC supports only ULPI interface and has the OTG capability. U2D Controller ULPI driver introduced in this patch supports only the PXA310 USB Host via the ULPI. Signed-off-by: NIgor Grinberg <grinberg@compulab.co.il> Signed-off-by: NMike Rapoport <mike@compulab.co.il> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
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- 30 9月, 2010 1 次提交
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由 Robert Richter 提交于
This patch fixes a resource leak on failure, where the oprofilefs and some counters may not released properly. Signed-off-by: NRobert Richter <robert.richter@amd.com> Acked-by: NWill Deacon <will.deacon@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: <stable@kernel.org> # .35.x LKML-Reference: <20100929145225.GJ13563@erda.amd.com> Signed-off-by: NIngo Molnar <mingo@elte.hu>
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- 27 9月, 2010 1 次提交
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由 Will Deacon 提交于
The PL310 on the ct-ca9x4 tile for the Versatile Express does not need to add additional latency when accessing its cache RAMs. Unfortunately, the boot monitor sets this up for an 8-cycle delay on reads and writes, resulting in greatly reduced memory performance when the L2 cache is enabled. This patch sets the L2 RAM latencies to the correct value of 1 cycle on the ct-ca9x4 tile before enabling the L2 cache. Acked-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 25 9月, 2010 8 次提交
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由 Santosh Shilimkar 提交于
On Davinci SRAM is mapped as MT_DEVICE becasue of the section mapping pre-requisite instead of intended MT_MEMORY_NONCACHED Since the section mapping limitation gets fixed with first patch in this series, the MT_MEMORY_NONCACHED can be used now. Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: NKevin Hilman <khilman@deeprootsystems.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Santosh Shilimkar 提交于
Currently we map 1 MB section while setting up SRAM on OMAPs Regardless of the actual memory. The physical OCM RAM available on OMAP SOCs is in order of KBs. This patch maps only available sram and cleans up some un-necessary cpu_is_xxx checks. Mapping un-available or non-accessible(secure) memory on the newer ARM processor is dangerous. Because ARM CPUs can now speculatively prefetch, we should avoid mapping any no-existing or secure memory. Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Santosh Shilimkar 提交于
This patch populates the L1 entries for MT_MEMORY and MT_MEMORY_NONCACHED types so that at boot-up, we can map memories outside system memory at page level granularity Previously the mapping was limiting to section level, which creates unnecessary additional mapping for which physical memory may not present. On the newer ARM with speculation, this is dangerous and can result in untraceable aborts. Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Joe Perches 提交于
Signed-off-by: NJoe Perches <joe@perches.com> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
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由 Eric Miao 提交于
When CONFIG_PXA3xx is not selected, cpu_is_pxa3xx() doesn't expand to zero, which in some places doesn't result in correct optimization. Signed-off-by: NEric Miao <eric.y.miao@gmail.com> Reported-and-tested-by: NMarek Vasut <marek.vasut@gmail.com>
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由 Mark F. Brown 提交于
Reset vector for pxa168 is 0xffff_0000 not 0x0. This fix allows reboot to work Signed-off-by: NMark F. Brown <mark.brown314@gmail.com> Signed-off-by: NEric Miao <eric.y.miao@gmail.com>
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由 Marek Vasut 提交于
Original idea by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
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由 Marek Vasut 提交于
GPIO 0 is valid, yet this platform doesn't have any power GPIO for MMC. Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
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- 24 9月, 2010 1 次提交
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由 Scott Ellis 提交于
Looks like a typo from commit d6d834b0. Signed-off-by: NScott Ellis <scott@jumpnowtek.com> Acked-by: NPeter Ujfalusi <peter.ujfalusi@nokia.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 23 9月, 2010 3 次提交
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由 Nicolas Pitre 提交于
When the policy for user space is to ignore misaligned accesses from user space, the processor then performs a documented rotation on the accessed data. This is the result of the access being trapped, and the kernel disabling the alignment trap before returning to user space again. In kernel space we always want misaligned accesses to be fixed up. This is enforced by always re-enabling the alignment trap on every entry into kernel space from user space. No such re-enabling is performed when an exception occurs while already in kernel space as the alignment trap is always supposed to be enabled in that case. There is however a small race window when a misaligned access in user space is trapped and the alignment trap disabled, but the CPU didn't return to user space just yet. Any exception would be entered from kernel space at that point and the kernel would then execute with the alignment trap disabled. Thanks to Maxime Bizon <mbizon@freebox.fr> for providing a test module that made this issue reproducible. Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Peter Korsgaard 提交于
Use a correct udelay value to get bus speed around 100KHz. The udelay value was most likely copied from the older devices, but the 9g45 is signicantly faster (400MHz, DDR, ..), so a udelay of 2 gives a bus speed of around 190KHz, which is too fast for some devices. A udelay value of 5 gives a bus speed of around 90KHz here. Signed-off-by: NPeter Korsgaard <jacmet@sunsite.dk> Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 FUJITA Tomonori 提交于
This fixes the regression caused by the commit 6fee48cd ("dma-mapping: arm: use generic pci_set_dma_mask and pci_set_consistent_dma_mask"). ARM needs to clip the dma coherent mask for dmabounce devices. This restores the old trick. Note that strictly speaking, the DMA API doesn't allow architectures to do such but I'm not sure it's worth adding the new API to set the dma mask that allows architectures to clip it. Reported-by: NKrzysztof Halasa <khc@pm.waw.pl> Signed-off-by: NFUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Acked-by: NRussell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 20 9月, 2010 2 次提交
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由 Eric Miao 提交于
Signed-off-by: NEric Miao <eric.miao@canonical.com> Acked-by: NSaeed Bishara <saeed@marvell.com> Signed-off-by: NNicolas Pitre <nico@fluxnic.net>
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由 Arnaud Patard 提交于
The support for the 2 pcie port of the 6282 has broken i/o port by switching *_IO_PHYS_BASE and *_IO_BUS_BASE. In fact, the patches reintroduced the same bug solved by commit 35f029e2. So, I'm adding back *_IO_BUS_BASE in resource declaration and fix definition of KIRKWOOD_PCIE1_IO_BUS_BASE. With this change, the xgi card on my t5325 is working again. Signed-off-by: NArnaud Patard <arnaud.patard@rtp-net.org> Acked-by: NSaeed Bishara <saeed@marvell.com> Signed-off-by: NNicolas Pitre <nico@fluxnic.net> Cc: stable@kernel.org
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- 19 9月, 2010 3 次提交
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由 Russell King 提交于
Jonathan Cameron reports that when using the environment variable KCONFIG_CONFIG, he encounters this error: make[2]: *** No rule to make target `.config', needed by `arch/arm/boot/compressed/vmlinux.lds' Reported-by: NJonathan Cameron <jic23@cam.ac.uk> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Catalin Marinas 提交于
ARMv7 onwards requires that there are no aliases to the same physical location using different memory types (i.e. Normal vs Strongly Ordered). Access to SO mappings when the unaligned accesses are handled in hardware is also Unpredictable (pgprot_noncached() mappings in user space). The /dev/mem driver requires uncached mappings with O_SYNC. The patch implements the phys_mem_access_prot() function which generates Strongly Ordered memory attributes if !pfn_valid() (independent of O_SYNC) and Normal Noncacheable (writecombine) if O_SYNC. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Peter Korsgaard 提交于
5cfc8ee0 (ARM: convert arm to arch_gettimeoffset()) marked all of at91 AND at91x40 as needing ARCH_USES_GETTIMEOFFSET, and hence no high res timer support / accurate clock_gettime() - But only at91x40 needs it. Cc: stable@kernel.org Signed-off-by: NPeter Korsgaard <peter.korsgaard@barco.com> Acked-by: NJohn Stultz <johnstul@us.ibm.com> Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 18 9月, 2010 4 次提交
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由 Darius Augulis 提交于
Add IORESOURCE_IRQ_HIGHLEVEL irq flag to dm9000 driver platform data in board mach-real6410. Signed-off-by: NDarius Augulis <augulis.darius@gmail.com> [kgene.kim@samsung.com: minor title fix] Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Darius Augulis 提交于
Fix errors reported by checkpatch.pl script Signed-off-by: NDarius Augulis <augulis.darius@gmail.com> [kgene.kim@samsung.com: minor title fix] Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Mark Brown 提交于
Avoids build warnings due to the undeclared non-statics. Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Al Viro 提交于
If a signal hits us outside of a syscall and another gets delivered when we are in sigreturn (e.g. because it had been in sa_mask for the first one and got sent to us while we'd been in the first handler), we have a chance of returning from the second handler to location one insn prior to where we ought to return. If r0 happens to contain -513 (-ERESTARTNOINTR), sigreturn will get confused into doing restart syscall song and dance. Incredible joy to debug, since it manifests as random, infrequent and very hard to reproduce double execution of instructions in userland code... The fix is simple - mark it "don't bother with restarts" in wrapper, i.e. set r8 to 0 in sys_sigreturn and sys_rt_sigreturn wrappers, suppressing the syscall restart handling on return from these guys. They can't legitimately return a restart-worthy error anyway. Testcase: #include <unistd.h> #include <signal.h> #include <stdlib.h> #include <sys/time.h> #include <errno.h> void f(int n) { __asm__ __volatile__( "ldr r0, [%0]\n" "b 1f\n" "b 2f\n" "1:b .\n" "2:\n" : : "r"(&n)); } void handler1(int sig) { } void handler2(int sig) { raise(1); } void handler3(int sig) { exit(0); } main() { struct sigaction s = {.sa_handler = handler2}; struct itimerval t1 = { .it_value = {1} }; struct itimerval t2 = { .it_value = {2} }; signal(1, handler1); sigemptyset(&s.sa_mask); sigaddset(&s.sa_mask, 1); sigaction(SIGALRM, &s, NULL); signal(SIGVTALRM, handler3); setitimer(ITIMER_REAL, &t1, NULL); setitimer(ITIMER_VIRTUAL, &t2, NULL); f(-513); /* -ERESTARTNOINTR */ write(1, "buggered\n", 9); return 1; } Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk> Acked-by: NRussell King <rmk+kernel@arm.linux.org.uk> Cc: stable@kernel.org Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 17 9月, 2010 9 次提交
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由 Daniel Walker 提交于
Setting of these bits can cause issues on other SMP SoC's not produced by ARM. Acked-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
Al Viro reports that calling "sys_sigsuspend(-ERESTARTNOHAND, 0, 0)" with two signals coming and being handled in kernel space results in the syscall restart being done twice. Avoid this by clearing the 'why' flag when we call the signal handling code to prevent further syscall restarts after the first. Acked-by: NAl Viro <viro@zeniv.linux.org.uk> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Catalin Marinas 提交于
Clearing bit 22 in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. Cc: Nicolas Pitre <nicolas.pitre@linaro.org> Cc: <stable@kernel.org> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Will Deacon 提交于
On the r2p0, r2p1 and r2p2 versions of the Cortex-A9, data corruption can occur if a shared cache line is replaced on one CPU as another CPU is accessing it. This workaround sets two bits in the diagnostic register of the Cortex-A9, reducing the linefill issuing capabilities of the processor and avoiding the erroneous behaviour. Acked-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Will Deacon 提交于
On versions of the Cortex-A9 up to and including r2p2, under rare circumstances, a DMB instruction between 2 write operations may not ensure the correct visibility ordering of the 2 writes. This workaround sets a bit in the diagnostic register of the Cortex-A9, causing the DMB instruction to behave like a DSB, which functions correctly on the affected cores. Acked-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Will Deacon 提交于
Kconfig doesn't have any knowledge of specific v7 cores, so it is possible to select errata workarounds that may cause inadvertent behaviour when executed on a core other than those targetted by the fix. This patch improves the variant and revision checking in proc-v7.S so that the primary part number is also considered when applying errata workarounds. Acked-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Linus Walleij 提交于
We have to use _cansleep gpio accessors in the MMCI driver so as to avoid slowpath warnings, now U300 has MMCI but doesn't have these functions in place to siply wrap the existing non-sleeping functions into sleepable variants. Signed-off-by: NLinus Walleij <linus.walleij@stericsson.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Linus Walleij 提交于
The prescaler 16 is now used only when the timer runs at 32 MHz or more. Some comment updates as well. Acked-by: NAlessandro Rubini <rubini@unipv.it> Signed-off-by: NJonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: NLinus Walleij <linus.walleij@stericsson.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Linus Walleij 提交于
timer0 to 3 are all on mtu block 0, so don't calculate the clock event rate based upon mtu block 1's clock speed. Acked-by: NAlessandro Rubini <rubini@unipv.it> Signed-off-by: NJonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: NLinus Walleij <linus.walleij@stericsson.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 16 9月, 2010 1 次提交
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由 Tony Lindgren 提交于
If we LEDS_CLASS is not selected, we will get undefined reference to `led_classdev_register'. Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 14 9月, 2010 4 次提交
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由 Mark Brown 提交于
The irqs.h usage here got missed in the Samsung platform reorganisation. Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: NJassi Brar <jassi.brar@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Kukjin Kim 提交于
This patch fixes bug on gpio drive strength helper function. The offset should be like follwoing. - off = chip->chip.base - pin; + off = pin - chip->chip.base; In the s5p_gpio_get_drvstr(), the second line is unnecessary, because overwrite drvstr. drvstr = __raw_readl(reg); - drvstr = 0xffff & (0x3 << shift); And need 2bit masking before return the drvstr value. drvstr = drvstr >> shift; + drvstr &= 0x3; In the s5p_gpio_set_drvstr(), need relevant bit clear. tmp = __raw_readl(reg); + tmp &= ~(0x3 << shift); tmp |= drvstr << shift; Reported-by: NJaecheol Lee <jc.lee@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Kukjin Kim 提交于
This patch fixes on defined drive strength value for GPIO. According to data sheet, if we want drive strength 1x, the value should be 00(b), if 2x should be 10(b), if 3x should be 01(b), and if 4x should be 11(b). Also fixes comment(from S5C to S5P). Reported-by: NJanghyuck Kim <janghyuck.kim@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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由 Marek Szyprowski 提交于
These clocks enables FIMC driver to operate on machines, which bootloader power gated FIMC devices to save power on boot. Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> [kgene.kim@samsung.com: minor title fix] Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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