- 07 10月, 2021 7 次提交
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由 Jimmy Kizito 提交于
[Why & How] Additional debug flags that can be useful for testing USB4 DP link training. Add flags: - 0x2 : Forces USB4 DP link to non-LTTPR mode - 0x4 : Extends status read intervals to about 60s. Reviewed-by: NMeenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NWayne Lin <Wayne.Lin@amd.com> Acked-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NJimmy Kizito <Jimmy.Kizito@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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[Why & How] To add support for dpia debug options. Reviewed-by: NJimmy Kizito <Jimmy.Kizito@amd.com> Acked-by: NWayne Lin <Wayne.Lin@amd.com> Acked-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NMeenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Jimmy Kizito 提交于
[Why] We requires information from DPCD in order to identify USB4 DP tunneling targets. [How] Add USB4 DP tunneling fields to DPCD struct and populate these fields during sink detection. Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NWayne Lin <Wayne.Lin@amd.com> Acked-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NJimmy Kizito <Jimmy.Kizito@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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[Why] To process SET_CONFIG transactions with DMUB using inbox1 and outbox1 mail boxes. [How] 1) Added inbox1 DPIA command subtype DMUB_CMD__DPIA_SET_CONFIG_ACCESS to issue SET_CONFIG command to DMUB in dc_process_dmub_set_config_async(). DMUB processes the command with DPIA sends reply back immediately or in an outbox1 message triggering an outbox1 interrupt to driver. 2) DMUB posts SET_CONFIG reply as an Outbox1 message of type DMUB_OUT_CMD__SET_CONFIG_REPLY. 3) The dmub async to sync mechanism for AUX is modified to accommodate SET_CONFIG commands for both command issue and reply code paths. Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NWayne Lin <Wayne.Lin@amd.com> Acked-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NMeenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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[WHY] To add support for HPD & HPD RX interrupt handling for USB4 DPIA in YELLOW_CARP_B0. USB4 DPIA HPD & HPD RX interrupts are issued from DMUB to driver as a outbox1 message. [HOW] 1) Created get_link_index_from_dpia_port_index() to retrieve link index from dpia port index for HPD & HPD RX dmub notifications. 2) Added DMUB HPD & HPD RX handling in dmub_srv_stat_get_notification(). Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NWayne Lin <Wayne.Lin@amd.com> Acked-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NMeenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Aric Cyr 提交于
This version brings along following fixes: - New firmware version - Fix DMUB problems on stress test. - Improve link training by skip overrride for preferred link - Refinement of FPU code structure for DCN2 - Fix 3DLUT skipped programming - Fix detection of 4 lane for DPALT - Fix dcn3 failure due to dmcbu_abm not created - Limit display scaling to up to 4k for DCN 3.1 - Add helper for blanking all dp displays Acked-by: NSolomon Chiu <solomon.chiu@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Jake Wang 提交于
[Why & How] Added root clock optimization debug flags for future debugging. Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: NSolomon Chiu <solomon.chiu@amd.com> Signed-off-by: NJake Wang <haonan.wang2@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 28 9月, 2021 3 次提交
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由 Aric Cyr 提交于
This version brings along following fixes: - Fixes to backlight, LUT, PPS, MST - Use correct vpg for 128b/132b encoding - Improved logging for VCP - Replace referral of dal with dc Acked-by: NAnson Jacob <Anson.Jacob@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 David Galiffi 提交于
[Why] Requested feature to assist with Thermal, Acoustic, Power, and Performance tuning. [How] Add a debug field that will override calculated minimum DRAM clock, if the debug value is larger than the calculate value. Reviewed-by: NAlvin Lee <Alvin.Lee2@amd.com> Acked-by: NAnson Jacob <Anson.Jacob@amd.com> Signed-off-by: NDavid Galiffi <David.Galiffi@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Eric Yang 提交于
[Why] To prevent unnecessary wake up of DMCUB when ABM is enabled without PSR enabled, driver will notify DMCUB to stop ABM's vertical interrupts if vsync is disabled and steady state is reached. [How] Send inbox message to notify ABM pause based on vsync on/off Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: NAnson Jacob <Anson.Jacob@amd.com> Signed-off-by: NEric Yang <Eric.Yang2@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 24 9月, 2021 2 次提交
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由 Aric Cyr 提交于
This new DC version brings improvements in the following areas: - New firmware version - Fix HPD problems on DCN2 - Fix generic encoder problems and null deferences - Adjust DCN301 watermark - Rework dynamic bpp for DCN3x - Improve link training fallback logic Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Aric Cyr 提交于
Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 15 9月, 2021 6 次提交
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由 Ian Chen 提交于
Reviewed-by: NWenjing Liu <Wenjing.Liu@amd.com> Acked-by: NMikita Lipski <mikita.lipski@amd.com> Signed-off-by: NIan Chen <ian.chen@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Michael Strauss 提交于
[WHY] Power down VPG and AFMT blocks when not in use [HOW] Create afmt31 and vpg31 structs and add necessary fields to reg list Reviewed-by: NEric Yang <eric.yang2@amd.com> Acked-by: NMikita Lipski <mikita.lipski@amd.com> Signed-off-by: NMichael Strauss <michael.strauss@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Aric Cyr 提交于
* Correct degamma coefficients * Optimize bandwidth on following fast update * Fix multiple memory leaks reported by coverity * Get backlight from PWM if DMCU is not initialized Acked-by: NMikita Lipski <mikita.lipski@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Eric Yang 提交于
[Why] When system is in Z10 HPD interrupts cannot fire, we may miss display configuration changes. [How] When Zstate is enabled, if DMUB indicate DCN has lost power, do a complete detection periodically. Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: NMikita Lipski <mikita.lipski@amd.com> Signed-off-by: NEric Yang <Eric.Yang2@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Aric Cyr 提交于
* coverity kernel memory leak fixes * NULL pointer dereference fixes * Add periodic detection when zstate is enabled * Fork thread to offload work of hpd_rx_irq Acked-by: NMikita Lipski <mikita.lipski@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Leo (Hanghong) Ma 提交于
This reverts commit "Revert "Add DPCD writes at key points" ". The following patch will fix the system hang issue. v2: squash in indentation warning fix Signed-off-by: NLeo (Hanghong) Ma <hanghong.ma@amd.com> Acked-by: NMikita Lipski <mikita.lipski@amd.com> Reviewed-by: NAric Cyr <aric.cyr@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 02 9月, 2021 2 次提交
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由 Aric Cyr 提交于
This version brings along following fixes: - FW promotion 0.0.80 - Add missing ABM register offsets - Fix in swizzle mode mapping - Emulated sink support for freesync - Improvoments in max target bpp Acked-by: NQingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Tested-by: NDaniel Wheeler <Daniel.Wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Fangzhi Zuo 提交于
1. Retrieve 128/132b link cap. 2. 128/132b link training and payload allocation. 3. UHBR10 link rate support. [squash in warning fixes - Alex] Signed-off-by: NFangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 17 8月, 2021 3 次提交
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由 Aric Cyr 提交于
This version brings along following fixes: - Ensure DCN save init registers after VM setup - Fix multi-display support for idle opt workqueue - Use vblank control events for PSR enable/disable - Create default dc_sink when fail reading EDID under MST Acked-by: NWayne Lin <wayne.lin@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Jake Wang 提交于
[Why] DM initializes VM context after DMCUB initialization. This results in loss of DCN_VM_CONTEXT registers after z10. [How] Notify DMCUB when VM setup is complete, and have DMCUB save init registers. v2: squash in CONFIG_DRM_AMD_DC_DCN3_1 fix Reviewed-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: NWayne Lin <wayne.lin@amd.com> Signed-off-by: NJake Wang <haonan.wang2@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Jake Wang 提交于
[Why] DM initializes VM context after DMCUB initialization. This results in loss of DCN_VM_CONTEXT registers after z10. [How] Notify DMCUB when VM setup is complete, and have DMCUB save init registers. v2: squash in CONFIG_DRM_AMD_DC_DCN3_1 fix Reviewed-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: NWayne Lin <wayne.lin@amd.com> Signed-off-by: NJake Wang <haonan.wang2@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 10 8月, 2021 1 次提交
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由 Anthony Koo 提交于
This version brings along following fixes: - Fix memory allocation in dm IRQ context to use GFP_ATOMIC - Increase timeout threshold for DMCUB reset - Clear GPINT after DMCUB has reset - Add AUX I2C tracing - Fix code commenting style - Some refactoring - Remove invalid assert for ODM + MPC case Reviewed-by: NWyatt Wood <Wyatt.Wood@amd.com> Acked-by: NAnson Jacob <Anson.Jacob@amd.com> Signed-off-by: NAnthony Koo <Anthony.Koo@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 06 8月, 2021 3 次提交
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由 Aric Cyr 提交于
Acked-by: NAurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Wesley Chalmers 提交于
[WHY] For DCN31 onward, LTTPR is to be enabled and set to Transparent by VBIOS. Driver is to assume that VBIOS has done this without needing to check the VBIOS interop bit. [HOW] Add LTTPR enable and interop VBIOS bits into dc->caps, and force-set the interop bit to true for DCN31+. Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NAurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: NWesley Chalmers <Wesley.Chalmers@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Wesley Chalmers 提交于
[WHY] For DCN31 onward, LTTPR is to be enabled and set to Transparent by VBIOS. Driver is to assume that VBIOS has done this without needing to check the VBIOS interop bit. [HOW] Add LTTPR enable and interop VBIOS bits into dc->caps, and force-set the interop bit to true for DCN31+. Reviewed-by: NJun Lei <Jun.Lei@amd.com> Acked-by: NAurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: NWesley Chalmers <Wesley.Chalmers@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 29 7月, 2021 2 次提交
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由 Aric Cyr 提交于
This version brings along following fixed: - Guard DST_Y_PREFETCH register overflow in DCN21 - Add missing DCN21 IP parameter - Fix PSR command version - Add ETW logging for AUX failures - Add ETW log to dmub_psr_get_state - Fixed EdidUtility build errors - Fix missing reg offset for the dmcub test debug registers - Adding update authentication interface - Remove unused functions of opm state query support - Always wait for update lock status - Refactor riommu invalidation wa - Ensure dentist display clock update finished in DCN20 Reviewed-by: NHsieh Mike <Mike.Hsieh@amd.com> Acked-by: NSolomon Chiu <solomon.chiu@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Mark Morra 提交于
[HOW] Added #ifdefs and refactored various parts of dc to allow dc_link to be built by AMD EDID UTILITY [WHY] dc_dsc was refactored moving some of the code that AMD EDID UTILITY needed to dc_link, so now dc_link needs to be included by AMD EDID UTILITY Squash in DCN config fix (Alex) Reviewed-by: NLeung Martin <Martin.Leung@amd.com> Acked-by: NSolomon Chiu <solomon.chiu@amd.com> Signed-off-by: NMark Morra <MarkAlbert.Morra@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 23 7月, 2021 3 次提交
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由 Eric Yang 提交于
[Why] PMFW message which previously thought to only control Z9 controls both Z9 and Z10. Also HW design team requested that Z9 must only be supported on eDP due to content protection interop. [How] Change zstate support condition to match updated policy Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NEric Yang <Eric.Yang2@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Aric Cyr 提交于
DC version 3.2.145 brings improvements in multiple areas. In summary, we highlight: - Code improvements for passive - Cursor manipulation enhancements - Expand debug in some areas - Fix problems in DML - Other minor code refactors Reviewed-by: NAnson Jacob <Anson.Jacob@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Aric Cyr 提交于
Reviewed-by: NShahin Khayyer <Shahin.Khayyer@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 22 7月, 2021 2 次提交
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由 Eric Yang 提交于
[Why] PMFW message which previously thought to only control Z9 controls both Z9 and Z10. Also HW design team requested that Z9 must only be supported on eDP due to content protection interop. [How] Change zstate support condition to match updated policy Reviewed-by: NNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NEric Yang <Eric.Yang2@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Aric Cyr 提交于
Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: NAric Cyr <aric.cyr@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 09 7月, 2021 1 次提交
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由 Aric Cyr 提交于
DC version 3.2.142 brings improvements in multiple areas. In summary, we highlight: - Freesync improvements - Remove unnecessary assert - Firmware release 0.0.72 - Improve the EDID manipulation and DML calculations Signed-off-by: NAric Cyr <aric.cyr@amd.com> Acked-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 30 6月, 2021 1 次提交
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由 Zhan Liu 提交于
[Why] Sometimes, DP receiver chip power-controlled externally by an Embedded Controller could be treated and used as eDP, if it drives mobile display. In this case, we shouldn't be doing power-sequencing, hence we can skip waiting for T7-ready and T9-ready." [How] Added a feature mask to enable eDP no power sequencing feature. To enable this, set 0x10 flag in amdgpu.dcfeaturemask on Linux command line. Signed-off-by: NZhan Liu <zhan.liu@amd.com> Reviewed-by: NNikola Cornij <Nikola.Cornij@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 23 6月, 2021 2 次提交
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由 Alex Deucher 提交于
No need for a separate flag now that DCN3.1 is not in bring up. Fold into DRM_AMD_DC_DCN like previous DCN IPs. Reviewed-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Aric Cyr 提交于
Signed-off-by: NAric Cyr <aric.cyr@amd.com> Acked-by: NBindu Ramamurthy <bindu.r@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 16 6月, 2021 2 次提交
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由 Aric Cyr 提交于
This version brings along following fixed: - LTTPR improvements - Backlight improvements - eDP hotplug detection Signed-off-by: NAric Cyr <aric.cyr@amd.com> Acked-by: NAnson Jacob <Anson.Jacob@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Yi-Ling Chen 提交于
[Why] Some custom platforms use eDP hotplug events to notify panel capability changes that should be reported [How] Add a DC config option that unblocks eDP hotplug events Signed-off-by: NYi-Ling Chen <Yi-Ling.Chen2@amd.com> Reviewed-by: NAric Cyr <Aric.Cyr@amd.com> Acked-by: NAnson Jacob <Anson.Jacob@amd.com> Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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