1. 16 11月, 2017 5 次提交
  2. 15 8月, 2017 1 次提交
    • T
      drm/i915/gvt: Fix guest i915 full ppgtt blocking issue · 6b3816d6
      Tina Zhang 提交于
      Guest i915 full ppgtt functionality was blocking by an issue, which would
      lead to gpu hardware hang. Guest i915 driver may update the ppgtt table
      just before this workload is going to be submitted to the hardware by
      device model. This case wasn't handled well by device model before, due
      to the small time window between removing old ppgtt entry and adding the
      new one. Errors occur when the workload is executed by hardware during
      that small time window. This patch is to remove this time window by adding
      the new ppgtt entry first and then remove the old one.
      
      Changes in v2:
      - Move VGT_CAPS_FULL_PPGTT introduction to patch 2/4. (Joonas)
      
      Changes since v2:
      - Divide the whole patch set into two separate patch series, with one
        patch in i915 side to check guest i915 full ppgtt capability and enable
        it when this capability is supported by the device model, and the other
        one in gvt side which fixs the blocking issue and enables the device
        model to provide the capability to guest. And this patch focuses on gvt
        side. (Joonas)
      - Change the title from "reorder the shadow ppgtt update process by adding
        entry first" to "Fix guest i915 full ppgtt blocking issue". (Tina)
      
      Changes since v3:
      - Rebase to the latest branch.
      
      Changes since v4:
      - Tested by Tina Zhang.
      
      Changes since v5:
      - Rebase to the latest branch.
      
      v6:
      - Update full 48bit ppgtt definition
      
      Cc: Tina Zhang <tina.zhang@intel.com>
      Signed-off-by: NTina Zhang <tina.zhang@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      6b3816d6
  3. 10 8月, 2017 1 次提交
  4. 02 8月, 2017 1 次提交
  5. 08 6月, 2017 1 次提交
    • F
      drm/i915/gvt: Refine virtual reset function · 615c16a9
      fred gao 提交于
      during the emulation of virtual reset:
      1. only reset the engine related mmio ending with MMIO
         offset Master_IRQ, not include display stuff.
      
      2. fences are not required to set default
         value as well to prevent screen flicking.
      
      this will fix the issue of Guest screen hang while running
      Force tdr in Linux guest.
      
      v2:
      - only reset the engine related mmio. (Zhenyu & Zhiyuan)
      v3:
      - IMR/Ring mode registers are not save/restored. (Changbin)
      v4:
      - redefine the MMIO reset offset for easy understanding. (Zhenyu)
      - pvinfo can be reset. (Zhenyu)
      v5:
      - add more comments for mmio reset. (Zhenyu)
      
      Cc: Changbin Du <changbin.du@intel.com>
      Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
      Cc: Lv zhiyuan <zhiyuan.lv@intel.com>
      Cc: Zhang Yulei <yulei.zhang@intel.com>
      Signed-off-by: Nfred gao <fred.gao@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      615c16a9
  6. 31 3月, 2017 1 次提交
  7. 30 3月, 2017 4 次提交
    • Z
      drm/i915/gvt: Activate/de-activate vGPU in mdev ops. · b79c52ae
      Zhi Wang 提交于
      This patch introduces two functions for activating/de-activating vGPU in
      mdev ops.
      
      A racing condition was found between virtual vblank emulation and KVGMT
      mdev release path. V-blank emulation will emulate and inject V-blank
      interrupt for every active vGPU with holding gvt->lock, while in mdev
      release path, it will directly release hypervisor handle without changing
      vGPU status or taking gvt->lock, so a kernel oops is encountered when
      vblank emulation is injecting a interrupt with a invalid hypervisor
      handle. (Reported by Terrence)
      
      To solve this problem, we factor out vGPU activation/de-activation from
      vGPU creation/destruction path and let KVMGT mdev release ops de-activate
      the vGPU before release hypervisor handle. Once a vGPU is de-activated,
      GVT-g will not emulate v-blank for it or touch the hypervisor handle.
      
      Fixes: 659643f7 ("drm/i915/gvt/kvmgt: add vfio/mdev support to KVMGT")
      Signed-off-by: NZhi Wang <zhi.a.wang@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      b79c52ae
    • P
      drm/i915/gvt: create an idle vGPU · afe04fbe
      Ping Gao 提交于
      vGPU resource is allocated by scheduler. To account for non-allocated
      free cycles, we create an idle vGPU as the placeholder similar to idle task
      concept, which is useful to handle some corner cases in scheduling policy.
      Signed-off-by: NPing Gao <ping.a.gao@intel.com>
      Reviewed-by: NKevin Tian <kevin.tian@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      afe04fbe
    • P
      drm/i915/gvt: define weight according to vGPU type · bc90d097
      Ping Gao 提交于
      The weight defines proportional control of physical GPU resource
      shared between vGPUs. So far the weight is tied to a specific vGPU
      type, i.e when creating multiple vGPUs with different types, they
      will inherit different weights.
      
      e.g. The weight of type GVTg_V5_2 is 8, the weight of type GVTg_V5_4
      is 4, so vGPU of type GVTg_V5_2 has double vGPU resource of vGPU type
      GVTg_V5_4.
      
      TODO: allow user control the weight setting in the future.
      Signed-off-by: NPing Gao <ping.a.gao@intel.com>
      Reviewed-by: NKevin Tian <kevin.tian@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      bc90d097
    • Z
      drm/i915/gvt: adjust mem size for low resolution type · bf39ec33
      Zhenyu Wang 提交于
      From commit d1a513be ("drm/i915/gvt: add resolution definition for vGPU
      type"), small type has been restricted to small resolution, so not
      require larger high GM size any more. Change to smaller 384M for more
      VM creation with vGPU enabled which still perform reasonable workload.
      
      Fixes: d1a513be ("drm/i915/gvt: add resolution definition for vGPU type")
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      bf39ec33
  8. 24 2月, 2017 1 次提交
  9. 23 2月, 2017 1 次提交
    • Z
      drm/i915/gvt: adjust to fixed vGPU types · 191020b6
      Zhenyu Wang 提交于
      Previous vGPU type create tried to determine vGPU type name e.g _1, _2
      based on the number of mdev devices can be created, but different type
      might have very different resource size depending on physical device.
      We need to split type name vs. actual mdev resource and create fixed
      vGPU type with determined size for consistence.
      
      With this we'd like to fix vGPU types for _1, _2, _4 and _8 now, each
      type has fixed defined resource size. Available mdev instances that could
      be created is determined by physical resource, and user should query
      for that before creating.
      
      Cc: Kevin Tian <kevin.tian@intel.com>
      Reviewed-by: NKevin Tian <kevin.tian@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      191020b6
  10. 17 2月, 2017 1 次提交
    • M
      drm/i915/gvt: introduced failsafe mode into vgpu · fd64be63
      Min He 提交于
      New failsafe mode is introduced, when we detect guest not supporting
      GVT-g.
      In failsafe mode, we will ignore all the MMIO and cfg space read/write
      from guest.
      
      This patch can fix the issue that when guest kernel or graphics driver
      version is too low, there will be a lot of kernel traces in host.
      
      V5: rebased onto latest gvt-staging
      V4: changed coding style by Zhenyu and Ping's advice
      V3: modified coding style and error messages according to Zhenyu's comment
      V2: 1) implemented MMIO/GTT/WP pages read/write logic; 2) used a unified
      function to enter failsafe mode
      Signed-off-by: NMin He <min.he@intel.com>
      Signed-off-by: NPei Zhang <pei.zhang@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      fd64be63
  11. 14 2月, 2017 1 次提交
  12. 07 2月, 2017 1 次提交
  13. 13 1月, 2017 3 次提交
    • C
      drm/i915/gvt: fix vGPU instance reuse issues by vGPU reset function · cfe65f40
      Changbin Du 提交于
      Our function tests found several issues related to reusing vGPU
      instance. They are qemu reboot failure, guest tdr after reboot, host
      hang when reboot guest. All these issues are caused by dirty status
      inherited from last VM.
      
      This patch fix all these issues by resetting a virtual GPU before VM
      use it. The reset logical is put into a low level function
      _intel_gvt_reset_vgpu(), which supports Device Model Level Reset, Full
      GT Reset and Per-Engine Reset.
      
      vGPU Device Model Level Reset (DMLR) simulates the PCI reset to reset
      the whole vGPU to default state as when it is created, including GTT,
      execlist, scratch pages, cfg space, mmio space, pvinfo page, scheduler
      and fence registers. The ultimate goal of vGPU DMLR is that reuse a
      vGPU instance by different virtual machines. When we reassign a vGPU
      to a virtual machine we must issue such reset first.
      
      Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines
      (Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec.
      Unlike the FLR, GT reset only reset particular resource of a vGPU per
      the reset request. Guest driver can issue a GT reset by programming
      the virtual GDRST register to reset specific virtual GPU engine or all
      engines.
      
      Since vGPU DMLR and GT reset can share some code so we implement both
      these two into one single function intel_gvt_reset_vgpu_locked(). The
      parameter dmlr is to identify if we will do FLR or GT reset. The
      parameter engine_mask is to specific the engines that need to be
      resetted. If value ALL_ENGINES is given for engine_mask, it means
      the caller requests a full gt reset that we will reset all virtual
      GPU engines.
      Signed-off-by: NChangbin Du <changbin.du@intel.com>
      Reviewed-by: NJike Song <jike.song@intel.com>
      Reviewed-by: NKevin Tian <kevin.tian@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      cfe65f40
    • C
      drm/i915/gvt: move mmio init/clean function to mmio.c · cdcc4347
      Changbin Du 提交于
      Move the mmio space inititation function setup_vgpu_mmio()
      and cleanup function clean_vgpu_mmio() in vgpu.c to dedicated
      source file mmio.c, and rename them as intel_vgpu_init_mmio()
      and intel_vgpu_clean_mmio() respectively.
      Signed-off-by: NChangbin Du <changbin.du@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      cdcc4347
    • C
      drm/i915/gvt: move cfg space inititation function to cfg_space.c · 536fc234
      Changbin Du 提交于
      Move the configuration space inititation function setup_vgpu_cfg_space()
      in vgpu.c to dedicated source file cfg_space.c, and rename the function
      as intel_vgpu_init_cfg_space().
      Signed-off-by: NChangbin Du <changbin.du@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      536fc234
  14. 09 1月, 2017 2 次提交
  15. 23 11月, 2016 1 次提交
  16. 14 11月, 2016 2 次提交
  17. 10 11月, 2016 3 次提交
  18. 27 10月, 2016 1 次提交
  19. 20 10月, 2016 1 次提交
    • Z
      drm/i915/gvt: clean up intel_gvt.h as interface for i915 core · feddf6e8
      Zhenyu Wang 提交于
      i915 core should only call functions and structures exposed through
      intel_gvt.h. Remove internal gvt.h and i915_pvinfo.h.
      
      Change for internal intel_gvt structure as private handler which
      not requires to expose gvt internal structure for i915 core.
      
      v2: Fix per Chris's comment
      - carefully handle dev_priv->gvt assignment
      - add necessary bracket for macro helper
      - forward declartion struct intel_gvt
      - keep free operation within same file handling alloc
      
      v3: fix use after free and remove intel_gvt.initialized
      
      v4: change to_gvt() to an inline
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      feddf6e8
  20. 14 10月, 2016 8 次提交