1. 12 7月, 2021 1 次提交
  2. 03 6月, 2021 2 次提交
  3. 10 3月, 2021 1 次提交
  4. 22 1月, 2021 1 次提交
  5. 30 10月, 2020 1 次提交
  6. 02 10月, 2020 1 次提交
  7. 30 9月, 2020 1 次提交
  8. 09 9月, 2020 1 次提交
  9. 10 7月, 2020 1 次提交
  10. 07 7月, 2020 1 次提交
  11. 30 4月, 2020 1 次提交
  12. 16 12月, 2019 1 次提交
  13. 15 11月, 2019 1 次提交
  14. 19 10月, 2019 8 次提交
  15. 15 10月, 2019 2 次提交
  16. 01 10月, 2019 1 次提交
  17. 02 8月, 2019 1 次提交
  18. 19 6月, 2019 1 次提交
  19. 31 1月, 2019 1 次提交
  20. 09 1月, 2019 1 次提交
    • L
      spi: atmel: Convert to use CS GPIO descriptors · efc92fbb
      Linus Walleij 提交于
      This converts the Atmel SPI master driver to use GPIO descriptors
      for chip select handling.
      
      The Atmel driver has duplicate code to look up and initialize CS
      GPIOs from the device tree, so this is removed. It further has code
      to retrieve a CS GPIO from .controller_data but this seems to be
      completely unused in the kernel (legacy codepath?) so I deleted
      this support. It keeps track of polarity when switching the CS, but
      this is not needed anymore since we moved this over to the gpiolib.
      
      The local handling of the "npcs_pin" (I guess this might mean
      "negative polarity chip select pin") is preserved, but I strongly
      suspect this can be switched over to handling by the core and
      using the SPI_MASTER_GPIO_SS flag on the master to assure that
      the additional CS handling in the driver is also done.
      
      Cc: Eugen Hristev <eugen.hristev@microchip.com>
      Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
      Cc: Radu Pirea <radu.pirea@microchip.com>
      Cc: Linuxarm <linuxarm@huawei.com>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      efc92fbb
  21. 05 9月, 2018 1 次提交
  22. 28 3月, 2018 1 次提交
  23. 27 2月, 2018 1 次提交
  24. 05 1月, 2018 1 次提交
  25. 19 12月, 2017 1 次提交
  26. 24 6月, 2017 1 次提交
    • C
      spi: atmel: fix corrupted data issue on SAM9 family SoCs · 7094576c
      Cyrille Pitchen 提交于
      This patch disables the use of the DMA for data transfer and forces the
      use of PIO transfers instead as a quick fixup to solve the cache aliasing
      issue on ARM9 based cores, which embeds a VIVT data cache.
      
      Indeed in the case of VIVT data caches, it is not safe to call dma_map_*()
      functions to map buffers for DMA transfers when those buffers have been
      allocated by vmalloc() or from any DMA-unsafe area.
      
      Further patches may propose a better solution based on the use of a bounce
      buffer at the SPI sub-system level but such solution needs more time to be
      discussed. Then the use of DMA transfers could be enabled again to improve
      the performances but before that, this patch already solves the issue.
      Signed-off-by: NCyrille Pitchen <cyrille.pitchen@microchip.com>
      Acked-by: NNicolas Ferre <nicolas.ferre@microchip.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      Cc: stable@vger.kernel.org
      7094576c
  27. 07 6月, 2017 1 次提交
  28. 19 4月, 2017 1 次提交
  29. 12 4月, 2017 1 次提交
  30. 25 11月, 2016 2 次提交