Add an initial node for the Adreno GPU.
Signed-off-by: NVivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: NJordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

Signed-off-by: NArchit Taneja <architt@codeaurora.org>
[Removed instances of mmagic clocks;
Use qcom,msm8996-smmu-v2 bindings]
Signed-off-by: NVivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

Add device node for display smmu, aka. mdp_smmu.
Signed-off-by: NArchit Taneja <architt@codeaurora.org>
Signed-off-by: NVivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

Add device node for graphics smmu, aka. adreno_smmu.
Signed-off-by: NJordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: NVivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

Specify the relative CPU capacity of all SDM845 AP cores.

The values were provided by Qualcomm engineers.
Signed-off-by: NMatthias Kaehlcke <mka@chromium.org>
Reviewed-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

The 8 CPU cores of the SDM845 are organized in two clusters of 4 big
("gold") and 4 little ("silver") cores. Add a cpu-map node to the DT
that describes this topology.
Signed-off-by: NMatthias Kaehlcke <mka@chromium.org>
Reviewed-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

Add 'bi_tcxo' as ref clock for the DSI PHYs, it was previously
hardcoded in the PLL 'driver' for the 10nm PHY.
Signed-off-by: NMatthias Kaehlcke <mka@chromium.org>
Reviewed-by: NDouglas Anderson <dianders@chromium.org>
Reviewed-by: NStephen Boyd <swboyd@chromium.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

Add 'xo_board' as ref clock for the DSI PHYs, it was previously
hardcoded in the PLL 'driver' for the 28nm PHY.
Signed-off-by: NMatthias Kaehlcke <mka@chromium.org>
Reviewed-by: NDouglas Anderson <dianders@chromium.org>
Reviewed-by: NStephen Boyd <swboyd@chromium.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

The temperature information from the temp-alarm block itself is very
coarse ("temperature is above/below trip points"). Provide the driver
with the die temperature channel of the ADC on the PMIC for more precise
readings.
Signed-off-by: NMatthias Kaehlcke <mka@chromium.org>
Reviewed-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

Add the Audio DSP (ADSP) and Compute DSP (CDSP) nodes for TrustZone
based remoteproc, supporting booting these cores on e.g. the MTP, and
enable the same for the MTP.
Tested-by: NSibi Sankar <sibis@codeaurora.org>
Reviewed-by: NSibi Sankar <sibis@codeaurora.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

Define the rmtfs memory node. As the memory region specified in version
10 of the memory map is only 1MB a chunk of unallocated memory is
chosen.
Tested-by: NSibi Sankar <sibis@codeaurora.org>
Reviewed-by: NSibi Sankar <sibis@codeaurora.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

Update existing and add missing regions to the reserved memory map, as
described in version 10.
Reviewed-by: NSibi Sankar <sibis@codeaurora.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

Wire up the reset controller in the Qcom UFS controller for the PHY.
This will be used to toggle PHY reset during initialization of the PHY.
Reviewed-by: NStephen Boyd <swboyd@chromium.org>
Signed-off-by: NEvan Green <evgreen@chromium.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

blsp1_i2c1 is at 0x0c175000
blsp2_i2c5 is at 0x0c1ba000 (the label is correct)

Fixes: 1e71d0c2 ("arm64: dts: qcom: msm8998: Enumerate i2c controllers")
Signed-off-by: NMarc Gonzalez <marc.w.gonzalez@free.fr>
Reviewed-by: NJeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

The compatible flag should be different for each board to match
with the dtb and to let the bootloader pick the appropriate dtb.
Signed-off-by: NKhasim Syed Mohammed <khasim.mohammed@linaro.org>
Signed-off-by: NNiklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

This adds the gpio-ranges property so that the GPIO pins are initialized
by the GPIO framework and not pinctrl. This fixes a circular dependency
between these two frameworks so GPIO hogging can be used on this board.

This was not tested on this particular hardware, however this same
change was tested on qcom-pm8941 using a LG Nexus 5 (hammerhead) phone.
Signed-off-by: NBrian Masney <masneyb@onstation.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

This adds the gpio-ranges property so that the GPIO pins are initialized
by the GPIO framework and not pinctrl. This fixes a circular dependency
between these two frameworks so GPIO hogging can be used on this board.

This was not tested on this particular hardware, however this same
change was tested on qcom-pm8941 using a LG Nexus 5 (hammerhead) phone.
Signed-off-by: NBrian Masney <masneyb@onstation.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

This adds the gpio-ranges property so that the GPIO pins are initialized
by the GPIO framework and not pinctrl. This fixes a circular dependency
between these two frameworks so GPIO hogging can be used on this board.

This was not tested on this particular hardware, however this same
change was tested on qcom-pm8941 using a LG Nexus 5 (hammerhead) phone.
Signed-off-by: NBrian Masney <masneyb@onstation.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

This adds the gpio-ranges property so that the GPIO pins are initialized
by the GPIO framework and not pinctrl. This fixes a circular dependency
between these two frameworks so GPIO hogging can be used on this board.

This was not tested on this particular hardware, however this same
change was tested on qcom-pm8941 using a LG Nexus 5 (hammerhead) phone.
Signed-off-by: NBrian Masney <masneyb@onstation.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

Fixup MSM8998 UFS DT nodes now that Evan's reset series has landed.
https://lore.kernel.org/lkml/20190321171800.104681-1-evgreen@chromium.org/Signed-off-by: NMarc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: NAndy Gross <agross@kernel.org>

We don't have any cooling-devices related to the camera. Use the "hot"
trip type so allow the temperature to be exported to userspace and
remove the "critical" trip.
Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

Maintain naming consistency with what was landed for sdm845. Simplifies
parsing for test tools.
Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

Maintain naming consistency with what was landed for sdm845. Simplifies
parsing for test tools.
Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

Maintain naming consistency with what was landed for sdm845. Simplifies
parsing for test tools.
Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

sdm845 has a total of 21 temperature sensors. Populate DT with
information about them.
Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

msm8998 has a total of 22 temperature sensors. Populate DT with
information about them.
Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

The first sensor is on top and the second sensor below the GPU
Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

The GPU sensor is sensor ID 13 on controller 0

Fixes: 4449b6f2 ("arm64: dts: qcom: msm8998: Add tsens and thermal-zones")
Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

The silver cluster (typically cpu0-3) are monitored by sensor IDs 1-3 on
tsens controller 0. The gold cluster (typically cpu4-7) are monitored by
sensor IDs 7-10 on tsens controller 0.

Fixes: 4449b6f2 ("arm64: dts: qcom: msm8998: Add tsens and thermal-zones")
Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

msm8996 has a total of 21 temperature sensors. Populate DT with
information about them.

There are 2 sensors on each of the cpus - one on the top, the other
below (we only expose one on the top in DT for now). For the GPU, we
expose both, the one on the top and the one below.

Depending on the version of the silicon, sensor 2 is either placed near
the L3 cache or the venus video decoder. It would've been nice to be
able to be version-specific but we don't have DTs that differentiate the
two versions of silicon yet.
Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

On platforms that have a modem, sensor 0 monitors the modem.
Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

efficiency comes from downstream. The valid upstream property is
capacity-dmips-mhz but until we can come up with those numbers, remove
this property.
Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

We've earlier added support to split the register address space into TM
and SROT regions. Split up the regmap address space into two for msm8998
that has a similar register layout.

The order is important (TM before SROT) because we make an assumption
that SROT is always the second address space in order to support legacy
DTs.
Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: NAndy Gross <agross@kernel.org>

In order to fix dependencies with rpmpd DT entries, the header was
dropped and hardcoded values were added for opp-level, during the
previous merge window.
Add the header back in now and remove the hardcodings, effectively
reverting commit '08585d21: arm64: dts:
sdm845: Fixup dependency on RPMPD includes'
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Enable blsp1_uart3, define its pinconf and add the bluetooth node.

It seems provisioning is lacking a valid BD address, preventing the
interface from initializing, so provide a dummy for now.
Tested-by: NVinod Koul <vkoul@kernel.org>
Reviewed-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Define the EVB pms405_s3 supplies.
Signed-off-by: NJorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: NKhasim Syed Mohammed <khasim.mohammed@linaro.org>
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

The PMS405 sports 5 SMPS and 13 LDO regulators, add the regulators to
pms405 DTS.
Signed-off-by: NJorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: NKhasim Syed Mohammed <khasim.mohammed@linaro.org>
Signed-off-by: NVinod Koul <vkoul@kernel.org>
[bjorn: updated label]
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Add host controller and PHY DT nodes.
Tested-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMarc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

The UFS host controller driver needs to set the load on 3 power rails
(l20, l26, s4) but the operation fails silently unless we specify the
regulator-allow-set-load property in the corresponding DT nodes.
Tested-by: NLee Jones <lee.jones@linaro.org>
Reviewed-by: NJeffrey Hugo <jhugo@codeaurora.org>
Signed-off-by: NMarc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>