Type A and B PLLs require a bit different calculations for the clock
rates. DPI driver supports only type A PLLs.

This patch adds support for the type B PLL.

Type B PLLs are simpler than type A, as type B can produce a good clock
for almost any rate. Thus we can just ask it to produce the pixel clock
and use one as LCK and PCK dividers.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Add comments showing how the PLL clock rates are calculated.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

dss_pll_calc_b() takes HDMI TMDS clock rate as a parameter. To make
dss_pll_calc_b() usable for non-HDMI users, change the function to take
clkout rate as parameter, and also change the current users of
dss_pll_calc_b() to accommodate that.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Move hdmi_pll_compute(), used to calculate the config for HDMI PLL, from
hdmi_pll.c to pll.c, with the name of dss_pll_calc_b(), to make it
available to non-HDMI users.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Add a "_a" postfix to the type A PLL calc functions, to differentiate
them from the type B PLL calculations which we will add shortly.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

To make it possible to use HDMI PLL for other video outputs than HDMI,
the HDMI PLL code needs to do runtime_get/put for the HDMI IP, so that
the IP (include the PLL) is enabled.

To do that we also need to store the HDMI pdev in the hdmi_pll_data.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

DPI driver uses a fixed clkout index, 0. This has worked fine as the
first clkout is usually used.

To generalize the code and to support additional clock sources, change
the code to use dss_pll_get_clkout_idx_for_src() to get the clkout
index.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

We can clean up the DPI driver's clock source handling by using the
dss_clk_source instead of only a dss_pll pointer.

This will also make it possible to use additional clock sources, like
PLL1_3 or HDMI_PLL, which the code did not support earlier.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

With the new PLL helpers, we can clean up the dispc_fclk_rate(). This
will also make dispc_fclk_rate() support clock sources it didn't support
earlier.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

With the new PLL helpers, we can clean up the dispc_mgr_lclk_rate().
This will also make dispc_mgr_lclk_rate() support clock sources it
didn't support earlier.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Add two PLL helper functions:

dss_pll_find_by_src() which returns the dss_pll for the given
dss_clk_source.

dss_pll_get_clkout_idx_for_src() which returns the clkout index for the
given dss_clk_source.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

The code to set the clock muxes for DISPC's LCD clock inputs is very
confusing. Especially on DRA7, there's an additional clock muxing that
needs to be done, which at the moment is done in dpi.c using
dss_ctrl_pll_set_control_mux().

Clean this all up by:
- Using dss_clk_source instead of dss_pll_id, as dss_pll_id doesn't
  specify the clock source quite correctly.
- Splitting the dss_select_lcd_clk_source() up into DSS version specific
  helper functions.
- Using dss_ctrl_pll_set_control_mux() from the helper functions, so
  that dpi.c doesn't have to call it.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

DSS uses two types of PLLs, type A (DSI & Video) and type B (HDMI). The
two types behave slightly differently, but we don't have the type of the
PLL available anywhere for the driver.

This patch adds an enum for the PLL type and a field in the PLL's HW
data to store it.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

enum dss_clk_source does not have values for all clock sources available
on OMAP4+ DSS versions. Add the missing clock sources.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

The names of the enum dss_clk_source's values are legacy names, only
correct for OMAP3 DSS. Rename the names to more generic ones.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Now that there is no "non-generic" version of the function to get the
clock source name, lets rename dss_get_generic_clk_source_name() to
dss_get_clk_source_name().
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

We have two functions to return a name for clock sources for debugging
purposes: dss_feat_get_clk_source_name() and
dss_get_generic_clk_source_name().

The former is supposed to return a DSS IP version specific name for the
clock source, and the latter is supposed to return a more generic name.

All this seems a bit pointless, so let's remove the former one.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

'enum omap_dss_clk_source' is internal to dss. Let's rename it to
'dss_clk_source' match our naming convention.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

At the moment 'enum omap_dss_clk_source' is in omapdss.h, shared by
omapdrm and omapfb. We're about to improve the omapdrm clock code, so we
need to make a separate copy of the enum for each driver.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Video pll hw data is missing bitfield definitions for clkout2 and
clkout3. We don't use those clkouts at the moment, so this has not
caused any issues.

Add the bitfields.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

'r' is supposed to be int, not u16, so fix it.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>

Switch the order of the loops to walk the rates on the top
so we exhaust all DP 1.1 rate/lane combinations before trying
DP 1.2 rate/lane combos.

This avoids selecting rates that are supported by the monitor,
but not the connector leading to valid modes getting rejected.

bug:
https://bugs.freedesktop.org/show_bug.cgi?id=95206Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

Switch the order of the loops to walk the rates on the top
so we exhaust all DP 1.1 rate/lane combinations before trying
DP 1.2 rate/lane combos.

This avoids selecting rates that are supported by the monitor,
but not the connector leading to valid modes getting rejected.

bug:
https://bugs.freedesktop.org/show_bug.cgi?id=95206Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

LPT is pch, so might run into the fdi bandwidth constraint (especially
since it has only 2 lanes). But right now we just force pipe_bpp back
to 24, resulting in a nice loop (which we bail out with a loud
WARN_ON). Fix this.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
References: https://bugs.freedesktop.org/show_bug.cgi?id=93477Signed-off-by: NDaniel Vetter <daniel.vetter@intel.com>
Tested-by: NChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: NMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1462264381-7573-1-git-send-email-daniel.vetter@ffwll.ch
(cherry picked from commit f58a1acc)
Signed-off-by: NJani Nikula <jani.nikula@intel.com>

On DCE6.1 PPLL2 is exclusively available to UNIPHYA, so it should not
be taken into consideration when looking for an already enabled PLL
to be shared with other outputs.

This fixes the broken VGA port (TRAVIS DP->VGA bridge) on my Richland
based laptop, where the internal display is connected to UNIPHYA through
a TRAVIS DP->LVDS bridge.

Bug:
https://bugs.freedesktop.org/show_bug.cgi?id=78987

v2: agd: add check in radeon_get_shared_nondp_ppll as well, drop
    extra parameter.
Signed-off-by: NLucas Stach <dev@lynxeye.de>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

There is an issue observed when we hotplug a second DP
4K monitor to the system. Sometimes, the link training
fails for the second monitor after HPD interrupt
generation.

The issue happens when some queued or deferred transactions
are already present on the AUX channel when we initiate
a new transcation to (say) get DPCD or during link training.

We set AUX_IGNORE_HPD_DISCON bit in the AUX_CONTROL
register so that we can ignore any such deferred
transactions when a new AUX transaction is initiated.
Signed-off-by: NArindam Nath <arindam.nath@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

Right now MST audio is causing too many kernel panics to really keep
around in the kernel. On top of that, even after fixing said panics it's
still basically non-functional (at least on all the setups I've tested
it on). Revert until we have a proper solution for this.

This reverts commit 3d52ccf5.
Signed-off-by: NLyude <cpaul@redhat.com>
Fixes: 3d52ccf5 ("drm/i915: start adding dp mst audio")
Cc: stable@vger.kernel.org
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1462287692-28570-1-git-send-email-cpaul@redhat.com
(cherry picked from commit 5a8f97ea)
Signed-off-by: NJani Nikula <jani.nikula@intel.com>

BSpec requires us to wait ~100 clocks before re-enabling clock gating,
so make sure we do this.

CC: stable@vger.kernel.org
CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: NImre Deak <imre.deak@intel.com>
Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1462280061-1457-2-git-send-email-imre.deak@intel.com
(cherry picked from commit 48e5d68d)
Signed-off-by: NJani Nikula <jani.nikula@intel.com>

The LVDS border enable is independent from the panel fitter. Move the
readout of the "border bits" from i9xx_get_pfit_config() to
intel_lvds_get_config(), where it will be read if LVDS is enabled even
if the panel fitter is not.

This fixes the state checker warning:

[drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in
gmch_pfit.lvds_border_bits (expected 0x00008000, found 0x00000000)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: drm-intel-fixes@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=87632Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: NSitsofe Wheeler <sitsofe@yahoo.com>
Signed-off-by: NJani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1461933243-2140-1-git-send-email-jani.nikula@intel.com
(cherry picked from commit a0cbe6a3)
Signed-off-by: NJani Nikula <jani.nikula@intel.com>

Update CDCLK_FREQ on BDW after changing the cdclk frequency. Not sure
if this is a late addition to the spec, or if I simply overlooked this
step when writing the original code.

This is what Bspec has to say about CDCLK_FREQ:
"Program this field to the CD clock frequency minus one. This is used to
 generate a divided down clock for miscellaneous timers in display."

And the "Broadwell Sequences for Changing CD Clock Frequency" section
clarifies this further:
"For CD clock 337.5 MHz, program 337 decimal.
 For CD clock 450 MHz, program 449 decimal.
 For CD clock 540 MHz, program 539 decimal.
 For CD clock 675 MHz, program 674 decimal."

Cc: stable@vger.kernel.org
Cc: Mika Kahola <mika.kahola@intel.com>
Fixes: b432e5cf ("drm/i915: BDW clock change support")
Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1461689194-6079-2-git-send-email-ville.syrjala@linux.intel.comReviewed-by: NMika Kahola <mika.kahola@intel.com>
(cherry picked from commit 7f1052a8)
Signed-off-by: NJani Nikula <jani.nikula@intel.com>

hw doesn't like a 0 value.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

hw doesn't like a 0 value.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

Without this there was a double free of the metadata,
which ended up freeing the fd table for me here, and taking
out the machine more often than not.

I reproduced with X.org + modesetting DDX + latest llvm/mesa,
also required using dri3.

Cc: stable@vger.kernel.org
Reviewed-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

mode->hdisplay * (var->bits_per_pixel + 7) gets evaluated before
the division, potentially making the pitch larger than it should
be.

Since the original intention is to do a div-round-up, just use
the macro instead.
Signed-off-by: NSinclair Yeh <syeh@vmware.com>
Reviewed-by: NThomas Hellstrom <thellstrom@vmware.com>

Instead of calling vmw_cmd_ok, call vmw_cmd_dx_cid_check to
validate the context id for query commands.
Signed-off-by: NCharmaine Lee <charmainel@vmware.com>
Reviewed-by: NSinclair Yeh <syeh@vmware.com>

Fixes piglit tests nv_conditional_render-* crashes.
Signed-off-by: NCharmaine Lee <charmainel@vmware.com>
Reviewed-by: NBrian Paul <brianp@vmware.com>
Reviewed-by: NSinclair Yeh <syeh@vmware.com>

V2: disable all vm interrupts in late_init()
Signed-off-by: NFlora Cui <Flora.Cui@amd.com>
Reviewed-by: NKen Wang <Qingqing.Wang@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

It will help identify problematic boards.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This reverts commit bedf2a65.

See the radeon revert for an extended description.

Cc: stable@vger.kernel.org

When crtc/timing is disabled on boot the dig block
should be stopped in order ignore timing from crtc,
reset the steering fifo otherwise we get display
corruption or hung in dp sst mode.

v2: agd: fix coding style
Signed-off-by: NVitaly Prosyak <vitaly.prosyak@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>