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  1. 06 7月, 2013 3 次提交
    • A
      drm/radeon: fix surface setup on r1xx · 67d5ced5
      由 Alex Deucher 提交于 
      r1xx asics have a slightly different surface register
setup compared to newer asics.  There is no specific
enable bit for macro tiling, rather, to disable macro
tiling, you need to set the surface pitch to 0.

With this fixed, the special rn50 handling can go.
Noticed-by: NMark Kettenis <mark.kettenis@xs4all.nl>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
      67d5ced5
    • A
      drm/radeon: add support for 3d perf states on older asics · edcaa5b1
      由 Alex Deucher 提交于 
      Certain older rv770 asics have both a performance and
a 3D performance state rather than just multiple performance
levels in the state power state.  The current code would
select the performance state rather than the 3D performance
state when the "performance" profile was selected.  This change
switches to the "balanced" profile by default which ends up being
the internal performance profile.  When the user selects the
"performance" profile, it selects the internal 3D performance
state so the user can select the higher performance modes.

For most asics this changes nothing.  For certain rv770 asics
with static performance and 3D performance states, this allows
you to select between then using by selecting the "balanced"
and "performance" dpm profiles.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
      edcaa5b1
    • A
      drm/radeon: set default clocks for SI when DPM is disabled · c6cf7777
      由 Alex Deucher 提交于 
      Fix patching of vddc values for SI and enable manually forcing
clocks to default levels as per NI.

This improves the out of the box performance with SI asics.
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
      c6cf7777
  3. 04 7月, 2013 5 次提交
  5. 03 7月, 2013 1 次提交
  7. 02 7月, 2013 13 次提交
  9. 01 7月, 2013 18 次提交