1. 23 3月, 2021 9 次提交
  2. 21 3月, 2021 7 次提交
    • V
      Revert "net: dsa: sja1105: Clear VLAN filtering offload netdev feature" · a1e6f641
      Vladimir Oltean 提交于
      This reverts commit e9bf9694.
      
      The topic of the reverted patch is the support for switches with global
      VLAN filtering, added by commit 061f6a50 ("net: dsa: Add
      ndo_vlan_rx_{add, kill}_vid implementation"). Be there a switch with 4
      ports swp0 -> swp3, and the following setup:
      
      ip link add br0 type bridge vlan_filtering 1
      ip link set swp0 master br0
      ip link set swp1 master br0
      
      What would happen with VLAN-tagged traffic received on standalone ports
      swp2 and swp3? Well, it would get dropped, were it not for the
      .ndo_vlan_rx_add_vid and .ndo_vlan_rx_kill_vid implementations (called
      from vlan_vid_add and vlan_vid_del respectively). Basically, for DSA
      switches where VLAN filtering is a global attribute, we enforce the
      standalone ports to have 'rx-vlan-filter: off [fixed]' in their ethtool
      features, which lets the user know that all VLAN-tagged packets that are
      not explicitly added in the RX filtering list are dropped.
      
      As for the sja1105 driver, at the time of the reverted patch, it was
      operating in a pretty handicapped mode when it had ports under a bridge
      with vlan_filtering=1. Specifically, it was unable to terminate traffic
      through the CPU port (for further explanation see "Traffic support" in
      Documentation/networking/dsa/sja1105.rst).
      
      However, since then, the sja1105 driver has made considerable progress,
      and that limitation is no longer as severe now. Specifically, since
      commit 2cafa72e ("net: dsa: sja1105: add a new
      best_effort_vlan_filtering devlink parameter"), the driver is able to
      perform CPU termination even when some ports are under bridges with
      vlan_filtering=1. Then, since commit 8841f6e6 ("net: dsa: sja1105:
      make devlink property best_effort_vlan_filtering true by default"), this
      even became the default operating mode.
      
      So we can now take advantage of the logic in the DSA core.
      Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      a1e6f641
    • H
      r8169: add support for ethtool get_ringparam · dc4aa50b
      Heiner Kallweit 提交于
      Add support for the ethtool get_ringparam operation.
      Signed-off-by: NHeiner Kallweit <hkallweit1@gmail.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      dc4aa50b
    • A
      net: ipa: update some comments in "ipa_data.h" · b259cc2a
      Alex Elder 提交于
      Fix/expand some comments in "ipa_data.h".
      Signed-off-by: NAlex Elder <elder@linaro.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      b259cc2a
    • A
      net: ipa: sequencer type is for TX endpoints only · 1690d8a7
      Alex Elder 提交于
      We only program the sequencer type for TX endpoints.  So move the
      definition of the sequencer type fields into the TX-specific portion
      of the endpoint configuration data.  There's no need to maintain
      this in the IPA structure; we can extract it from the configuration
      data it points to in the one spot it's needed.
      
      We previously specified the sequencer type for RX endpoints with
      INVALID values.  These are no longer needed, so get rid of them.
      Signed-off-by: NAlex Elder <elder@linaro.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      1690d8a7
    • A
      net: ipa: split sequencer type in two · 8ee5df65
      Alex Elder 提交于
      An IPA endpoint has a sequencer that must be configured based on how
      the endpoint is to be used.  Currently the IPA code programs the
      sequencer type by splitting a value into four 4-bit nibbles.  Doing
      that doesn't really add much value, and regardless, a better way of
      splitting the sequencer type is into two halves--the lower byte
      describing how normal packet processing is handled, and the next
      byte describing information about processing replicas.
      
      So split the sequencer type into two sub-parts:  the sequencer type
      and the replication sequencer type.  Define the values supported for
      the "main" sequencer type, and define the values supported for the
      replication part separately.
      
      In addition, the sequencer type names are quite verbose, encoding
      what the type includes, but also what it *excludes*.  Rename the
      sequencer types in a way that mainly describes the number of passes
      that a packet takes through the IPA processing pipeline, and how
      many of those passes end by supplying the processed packet to the
      microprocessor.
      
      The result expands the supported types beyond what is required for
      now, but simplifies the way these are defined.
      Signed-off-by: NAlex Elder <elder@linaro.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      8ee5df65
    • A
      net: ipa: implement MAX_READS_BEATS QSB data · b9aa0805
      Alex Elder 提交于
      Starting with IPA v4.0, a limit is placed on the number of bytes
      outstanding in a transaction, to reduce latency.  The limit is
      imposed only if this value is non-zero.
      
      We don't use a non-zero value for SC7180, but newer versions of IPA
      do.  Prepare for that by allowing a programmed value to be specified
      in the platform configuration data.
      Signed-off-by: NAlex Elder <elder@linaro.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      b9aa0805
    • A
      net: ipa: use configuration data for QSB settings · 8a81efac
      Alex Elder 提交于
      Use the QSB configuration data in ipa_hardware_config_qsb(), rather
      than determining in code what values to use based on IPA version.
      Pass configuration data to ipa_hardware_config() so it can be passed
      to ipa_hardware_config_qsb().
      Signed-off-by: NAlex Elder <elder@linaro.org>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      8a81efac
  3. 20 3月, 2021 24 次提交