1. 03 7月, 2006 1 次提交
  2. 01 7月, 2006 1 次提交
  3. 30 6月, 2006 1 次提交
    • I
      [PATCH] genirq: rename desc->handler to desc->chip · d1bef4ed
      Ingo Molnar 提交于
      This patch-queue improves the generic IRQ layer to be truly generic, by adding
      various abstractions and features to it, without impacting existing
      functionality.
      
      While the queue can be best described as "fix and improve everything in the
      generic IRQ layer that we could think of", and thus it consists of many
      smaller features and lots of cleanups, the one feature that stands out most is
      the new 'irq chip' abstraction.
      
      The irq-chip abstraction is about describing and coding and IRQ controller
      driver by mapping its raw hardware capabilities [and quirks, if needed] in a
      straightforward way, without having to think about "IRQ flow"
      (level/edge/etc.) type of details.
      
      This stands in contrast with the current 'irq-type' model of genirq
      architectures, which 'mixes' raw hardware capabilities with 'flow' details.
      The patchset supports both types of irq controller designs at once, and
      converts i386 and x86_64 to the new irq-chip design.
      
      As a bonus side-effect of the irq-chip approach, chained interrupt controllers
      (master/slave PIC constructs, etc.) are now supported by design as well.
      
      The end result of this patchset intends to be simpler architecture-level code
      and more consolidation between architectures.
      
      We reused many bits of code and many concepts from Russell King's ARM IRQ
      layer, the merging of which was one of the motivations for this patchset.
      
      This patch:
      
      rename desc->handler to desc->chip.
      
      Originally i did not want to do this, because it's a big patch.  But having
      both "desc->handler", "desc->handle_irq" and "action->handler" caused a
      large degree of confusion and made the code appear alot less clean than it
      truly is.
      
      I have also attempted a dual approach as well by introducing a
      desc->chip alias - but that just wasnt robust enough and broke
      frequently.
      
      So lets get over with this quickly.  The conversion was done automatically
      via scripts and converts all the code in the kernel.
      
      This renaming patch is the first one amongst the patches, so that the
      remaining patches can stay flexible and can be merged and split up
      without having some big monolithic patch act as a merge barrier.
      
      [akpm@osdl.org: build fix]
      [akpm@osdl.org: another build fix]
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      d1bef4ed
  4. 26 6月, 2006 1 次提交
  5. 21 6月, 2006 2 次提交
  6. 29 3月, 2006 1 次提交
  7. 27 3月, 2006 3 次提交
  8. 09 1月, 2006 1 次提交
  9. 01 11月, 2005 2 次提交
  10. 09 9月, 2005 1 次提交
    • A
      [PATCH] ppc64: fix IPI on bpa_iic · a84195f3
      Arnd Bergmann 提交于
      This fixes a severe bug in the bpa_iic driver that caused
      all sorts of problems.
      
      We had been using incorrect priority values for inter processor
      interrupts, which resulted in always doing CALL_FUNCTION
      instead of RESCHEDULE or DEBUGGER_BREAK.
      
      The symptoms cured by this patch include bad performance on
      SMP systems spurious kernel panics in the IPI code.
      Signed-off-by: NArnd Bergmann <arndb@de.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      a84195f3
  11. 23 6月, 2005 1 次提交
    • A
      [PATCH] ppc64: Add driver for BPA interrupt controllers · cebf589c
      Arnd Bergmann 提交于
      Add support for the integrated interrupt controller on BPA
      CPUs. There is one of those for each SMT thread.
      
      The mapping of interrupt numbers to HW interrupt sources
      is described in arch/ppc64/kernel/bpa_iic.h.
      
      This version hardcodes the 'Spider' chip as the secondary
      interrupt controller. That is not really generic for the
      architecture, but at the moment it is the only secondary
      PIC that exists.
      
      A little more work will be needed on this as soon as
      we have boards with multiple external interrupt controllers.
      Signed-off-by: NArnd Bergmann <arndb@de.ibm.com>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      cebf589c