1. 06 1月, 2021 1 次提交
  2. 12 11月, 2020 1 次提交
  3. 10 11月, 2020 1 次提交
    • C
      drm/i915/gvt: Fix virtual display setup for BXT/APL · a5a8ef93
      Colin Xu 提交于
      Program display related vregs to proper value at initialization, setup
      virtual monitor and hotplug.
      
      vGPU virtual display vregs inherit the value from pregs. The virtual DP
      monitor is always setup on PORT_B for BXT/APL. However the host may
      connect monitor on other PORT or without any monitor connected. Without
      properly setup PIPE/DDI/PLL related vregs, guest driver may not setup
      the virutal display as expected, and the guest desktop may not be
      created.
      Since only one virtual display is supported, enable PIPE_A only. And
      enable transcoder/DDI/PLL based on which port is setup for BXT/APL.
      
      V2:
      Revise commit message.
      
      V3:
      set_edid should on PORT_B for BXT.
      Inject hpd event for BXT.
      
      V4:
      Temporarily disable vfio edid on BXT/APL until issue fixed.
      
      V5:
      Rebase to use new HPD define GEN8_DE_PORT_HOTPLUG for BXT.
      Put vfio edid disabling on BXT/APL to a separate patch.
      Acked-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      Signed-off-by: NColin Xu <colin.xu@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/20201109073922.757759-1-colin.xu@intel.com
      a5a8ef93
  4. 30 10月, 2020 2 次提交
  5. 03 6月, 2020 1 次提交
  6. 09 5月, 2020 1 次提交
  7. 17 3月, 2020 1 次提交
  8. 12 3月, 2020 1 次提交
  9. 06 3月, 2020 2 次提交
  10. 24 2月, 2020 2 次提交
  11. 04 4月, 2019 1 次提交
  12. 29 3月, 2019 1 次提交
    • C
      drm/i915/gvt: Enable async flip on plane surface mmio writes · d57b39e3
      Colin Xu 提交于
      According to Intel GFX PRM on 01.org, plane surface address can be updated
      synchronously or asynchronously. Synchronous flip will hold plane surface
      address update to start of next vsync, which is current implementation.
      Asynchronous flip will update the address as soon as possible. Without
      async flip, some 3D application could not reach better performance and
      the maximum performance is no higher than vsync frequency.
      
      The patch enables the async flip on plane surface address mmio update,
      and increment flip count correctly.
      
      With async flip enabled, some 3D applications have significant performance
      improvement. i.e. 3DMark Ice Storm has a 300%~400% increment on score.
      
      v2:
      Use bit operation definition for flip mode. (zhenyu)
      Reviewed-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      Signed-off-by: NColin Xu <colin.xu@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      d57b39e3
  13. 31 1月, 2019 2 次提交
  14. 10 1月, 2019 1 次提交
  15. 07 8月, 2018 1 次提交
  16. 02 7月, 2018 1 次提交
    • X
      drm/i915/gvt: changed DDI mode emulation type · a4cae23c
      Xiaolin Zhang 提交于
      changed gvt display transcode DDI mode from DP_SST to
      DVI to address below calltrace issue during guest booting
      up which is caused by zero dotclock initial value with DP_SST
      mode. transcode DVI mode emulation also align with native with DP
      connection.
      
      [drm:drm_calc_timestamping_constants]
      ERROR crtc 41: Can't calculate constants, dotclock = 0!
      
      WARNING: at drivers/gpu/drm/drm_vblank.c:620
      drm_calc_vbltimestamp_from_scanoutpos
      
      Call Trace:
      ? drm_calc_timestamping_constants+0x144/0x150 [drm]
      drm_get_last_vbltimestamp+0x54/0x90 [drm]
      drm_reset_vblank_timestamp+0x59/0xd0 [drm]
      drm_crtc_vblank_on+0x7b/0xd0 [drm]
      intel_modeset_setup_hw_state+0xb67/0xfd0 [i915]
      ? gen2_read32+0x110/0x110 [i915]
      ? drm_modeset_lock+0x30/0xa0 [drm]
      intel_modeset_init+0x794/0x19d0 [i915]
      ? intel_setup_gmbus+0x232/0x2e0 [i915]
      i915_driver_load+0xb4a/0xf40 [i915]
      Signed-off-by: NXiaolin Zhang <xiaolin.zhang@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      a4cae23c
  17. 13 6月, 2018 1 次提交
  18. 01 6月, 2018 1 次提交
  19. 18 5月, 2018 1 次提交
    • C
      drm/i915/gvt: Use vgpu_lock to protect per vgpu access · f25a49ab
      Colin Xu 提交于
      The patch set splits out 2 small locks from the original big gvt lock:
        - vgpu_lock protects per-vGPU data and logic, especially the vGPU
          trap emulation path.
        - sched_lock protects gvt scheudler structure, context schedule logic
          and vGPU's schedule data.
      
      Use vgpu_lock to replace the gvt big lock. By doing this, the
      mmio read/write trap path, vgpu virtual event emulation and other
      vgpu related process, would be protected under per vgpu_lock.
      
      v9:
        - Change commit author since the patches are improved a lot compared
          with original version.
          Original author: Pei Zhang <pei.zhang@intel.com>
        - Rebase to latest gvt-staging.
      v8:
        - Correct coding and comment style.
        - Rebase to latest gvt-staging.
      v7:
        - Remove gtt_lock since already proteced by gvt_lock and vgpu_lock.
        - Fix a typo in intel_gvt_deactivate_vgpu, unlock the wrong lock.
      v6:
        - Rebase to latest gvt-staging.
      v5:
        - Rebase to latest gvt-staging.
        - intel_vgpu_page_track_handler should use vgpu_lock.
      v4:
        - Rebase to latest gvt-staging.
        - Protect vgpu->active access with vgpu_lock.
        - Do not wait gpu idle in vgpu_lock.
      v3: update to latest code base
      v2: add gvt->lock in function gvt_check_vblank_emulation
      
      Performance comparison on Kabylake platform.
        - Configuration:
          Host: Ubuntu 16.04.
          Guest 1 & 2: Ubuntu 16.04.
      
      glmark2 score comparison:
        - Configuration:
          Host: glxgears.
          Guests: glmark2.
      +--------------------------------+-----------------+
      | Setup                          | glmark2 score   |
      +--------------------------------+-----------------+
      | unified lock, iommu=on         | 58~62 (avg. 60) |
      +--------------------------------+-----------------+
      | unified lock, iommu=igfx_off   | 57~61 (avg. 59) |
      +--------------------------------+-----------------+
      | per-logic lock, iommu=on       | 60~68 (avg. 64) |
      +--------------------------------+-----------------+
      | per-logic lock, iommu=igfx_off | 61~67 (avg. 64) |
      +--------------------------------+-----------------+
      
      lock_stat comparison:
        - Configuration:
          Stop lock stat immediately after boot up.
          Boot 2 VM Guests.
          Run glmark2 in guests.
          Start perf lock_stat for 20 seconds and stop again.
        - Legend: c - contentions; w - waittime-avg
      +------------+-----------------+-----------+---------------+------------+
      |            | gvt_lock        |sched_lock | vgpu_lock     | gtt_lock   |
      + lock type; +-----------------+-----------+---------------+------------+
      | iommu set  | c     | w       | c  | w    | c    | w      | c   | w    |
      +------------+-------+---------+----+------+------+--------+-----+------+
      | unified;   | 20697 | 839     |N/A | N/A  | N/A  | N/A    | N/A | N/A  |
      | on         |       |         |    |      |      |        |     |      |
      +------------+-------+---------+----+------+------+--------+-----+------+
      | unified;   | 21838 | 658.15  |N/A | N/A  | N/A  | N/A    | N/A | N/A  |
      | igfx_off   |       |         |    |      |      |        |     |      |
      +------------+-------+---------+----+------+------+--------+-----+------+
      | per-logic; | 1553  | 1599.96 |9458|429.97| 5846 | 274.33 | 0   | 0.00 |
      | on         |       |         |    |      |      |        |     |      |
      +------------+-------+---------+----+------+------+--------+-----+------+
      | per-logic; | 1911  | 1678.32 |8335|445.16| 5451 | 244.80 | 0   | 0.00 |
      | igfx_off   |       |         |    |      |      |        |     |      |
      +------------+-------+---------+----+------+------+--------+-----+------+
      Signed-off-by: NPei Zhang <pei.zhang@intel.com>
      Signed-off-by: NColin Xu <colin.xu@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      f25a49ab
  20. 30 3月, 2018 1 次提交
    • X
      drm/i915/gvt: Disable primary/sprite/cursor plane at virtual display initialization · 65eff272
      Xiong Zhang 提交于
      Much error exist in host dmesg during guest boot up with loca display
      enabled.
      gvt: vgpu 1: invalid range gmadr 0x0 size 0x0
      
      This error happens when qemu get dmabuf info in case that the virtual
      display plane is enabled but its base address is an invalid 0, such
      case may be true before guest enable its plane. At this moment, its
      state is copied from host where the plane may be enabled.
      
      This patch disable primary/sprite/cursor plane at virtual display
      initialization, so intel_vgpu_decode_primary/cursor/sprite could
      return early as plane is disabled, then plane base check is skipped and
      error message disapper.
      Signed-off-by: NXiong Zhang <xiong.y.zhang@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      65eff272
  21. 22 12月, 2017 2 次提交
  22. 11 12月, 2017 1 次提交
  23. 04 12月, 2017 1 次提交
    • T
      drm/i915/gvt: Add framebuffer decoder support · 9f31d106
      Tina Zhang 提交于
      This patch is to introduce the framebuffer decoder which can decode guest
      OS's framebuffer information, including primary, cursor and sprite plane.
      
      v16:
      - rebase to 4.14.0-rc6.
      
      v14:
      - refine pixel format table. (Zhenyu)
      
      v9:
      - move drm format change to a separate patch. (Xiaoguang)
      
      v8:
      - fix a bug in decoding primary plane. (Tina)
      
      v7:
      - refine framebuffer decoder code. (Zhenyu)
      Signed-off-by: NTina Zhang <tina.zhang@intel.com>
      Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      9f31d106
  24. 28 11月, 2017 1 次提交
    • X
      drm/i915/gvt: enabled pipe A default on creating vgpu · 7e605902
      Xiaolin Zhang 提交于
      when i915 driver unloading, it will shutdown all CRTCs and
      it will introudce kernel panic when conducting igt drv_module_reload
      test case under guest environment (bug reported by XENGT-468) as below:
      
      BUG: unable to handle kernel NULL pointer dereference at 0000000000000070
      IP: intel_edp_backlight_off+0xe/0x7c [i915]
      RIP: 0010:intel_edp_backlight_off+0xe/0x7c [i915]
      Call Trace:
       intel_disable_ddi+0xb3/0xbc [i915]
       intel_modeset_setup_hw_state+0x654/0xb4c [i915]
       intel_modeset_init+0x9f1/0xe69 [i915]
       ? intel_i2c_reset+0x3d/0x40 [i915]
       ? intel_setup_gmbus+0xba/0x249 [i915]
       i915_driver_load+0xae5/0xcc0 [i915]
       i915_pci_probe+0x3a/0x3c [i915]
       local_pci_probe+0x38/0x7b
       pci_device_probe+0xec/0x12b
       driver_probe_device+0x134/0x294
       __driver_attach+0x6a/0x8c
       ? driver_probe_device+0x294/0x294
       bus_for_each_dev+0x68/0x80
       driver_attach+0x19/0x1b
       bus_add_driver+0xea/0x1d3
       ? 0xffffffffa03cd000
       driver_register+0x85/0xc1
       ? 0xffffffffa03cd000
       __pci_register_driver+0x55/0x57
       i915_init+0x57/0x5a [i915]
       do_one_initcall+0x8a/0x12e
       ? __vunmap+0x8d/0x93
       ? kmem_cache_alloc_trace+0x96/0x11c
       do_init_module+0x5a/0x1e1
      
      in this case, active connector detected but no active pipe
      available, so it will hang to disable connector.
      
      to fix, on vgpu creating, to report active pipe available for
      guest.
      Signed-off-by: NXiaolin Zhang <xiaolin.zhang@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      7e605902
  25. 27 7月, 2017 1 次提交
  26. 17 7月, 2017 1 次提交
    • F
      drm/i915/gvt: Fix the vblank timer close issue after shutdown VMs in reverse · f43aa31f
      fred gao 提交于
      Once the Windows guest is shutdown, the display pipe will be disabled
      and intel_gvt_check_vblank_emulation will be called to check if the
      vblank timer is turned off. Given the scenario of creating VM1 ,VM2,
      destoying VM2 in current code, VM1 has pipe enabled and continues to
      check VM2, the flag have_enabled_pipe is always false since all the VM2
      pipes are disabled, so the vblank timer will be canceled and TDR happens
      in Windows VM1 guest due to the vsync timeout.
      
      In this patch the vblank timer will be never canceled once one pipe is
      enabled.
      
      v2:
      - remove have_enabled_pipe flag and check pipe enabled directly. (Zhenyu)
      
      Cc: Wang Hongbo <hongbo.wang@intel.com>
      Signed-off-by: Nfred gao <fred.gao@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      f43aa31f
  27. 27 6月, 2017 2 次提交
    • X
      drm/i915/gvt: Don't read ADPA_CRT_HOTPLUG_MONITOR from host · 75e64ff2
      Xiong Zhang 提交于
      When host connects a crt screen, linux guest will detect two
      screens: crt and dp. This is wrong as linux guest has only
      one dp.
      
      In order to avoid guest get host crt screen, we should set
      ADPA_CRT_HOTPLUG_MONITOR to none. But MMIO_RO(PCH_ADPA) prevent
      from that. So MMIO_DH should be used instead of MMIO_RO.
      
      v2: Clear its staus to none at initialize, so guest don't
          get host crt.(Zhangyu)
      v3: SKL doesn't have this register, limit it to pre_skl.(xiong)
      Signed-off-by: NXiong Zhang <xiong.y.zhang@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      75e64ff2
    • X
      drm/i915/gvt: Set initial PORT_CLK_SEL vreg for BDW · 295a0d0b
      Xiong Zhang 提交于
      On BDW, when host physical screen and guest virtual screen aren't on
      the same DDI port, guest i915 driver prints the following error and
      stop running.
      [    6.775873] BUG: unable to handle kernel NULL pointer dereference
      at 0000000000000068
      [    6.775928] IP: intel_ddi_clock_get+0x81/0x430 [i915]
      [    6.776206] Call Trace:
      [    6.776233]  ? vgpu_read32+0x4f/0x100 [i915]
      [    6.776264]  intel_ddi_get_config+0x11c/0x230 [i915]
      [    6.776298]  intel_modeset_setup_hw_state+0x313/0xd40 [i915]
      [    6.776334]  intel_modeset_init+0xe49/0x18d0 [i915]
      [    6.776368]  ? vgpu_write32+0x53/0x100 [i915]
      [    6.776731]  ? intel_i2c_reset+0x42/0x50 [i915]
      [    6.777085]  ? intel_setup_gmbus+0x32a/0x350 [i915]
      [    6.777427]  i915_driver_load+0xabc/0x14d0 [i915]
      [    6.777768]  i915_pci_probe+0x4f/0x70 [i915]
      
      The null pointer is guest intel_crtc_state->shared_dpll which is
      setted in haswell_get_ddi_pll(). When guest and host screen are
      on different DDI port, host driver won't set PORT_CLK_SET(guest_port),
      so haswell_get_ddi_pll() will return null and don't set
      pipe_config->shared_dpll, once the following program refernce this
      structure, it will print the above error.
      
      This patch set the initial val of guest PORT_CLK_SEL(guest_port) to
      LCPLL_810. And guest i915 driver will reset this value according to
      guest screen mode.
      Signed-off-by: NXiong Zhang <xiong.y.zhang@intel.com>
      Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com>
      295a0d0b
  28. 12 4月, 2017 1 次提交
  29. 29 3月, 2017 3 次提交
  30. 01 3月, 2017 1 次提交
  31. 24 2月, 2017 2 次提交