1. 29 3月, 2021 1 次提交
    • T
      MIPS/bpf: Enable bpf_probe_read{, str}() on MIPS again · 66633abd
      Tiezhu Yang 提交于
      After commit 0ebeea8c ("bpf: Restrict bpf_probe_read{, str}() only to
      archs where they work"), bpf_probe_read{, str}() functions were no longer
      available on MIPS, so there exist some errors when running bpf program:
      
      root@linux:/home/loongson/bcc# python examples/tracing/task_switch.py
      bpf: Failed to load program: Invalid argument
      [...]
      11: (85) call bpf_probe_read#4
      unknown func bpf_probe_read#4
      [...]
      Exception: Failed to load BPF program count_sched: Invalid argument
      
      ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE should be restricted to archs
      with non-overlapping address ranges, but they can overlap in EVA mode
      on MIPS, so select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA in
      arch/mips/Kconfig, otherwise the bpf old helper bpf_probe_read() will
      not be available.
      
      This is similar with the commit d195b1d1 ("powerpc/bpf: Enable
      bpf_probe_read{, str}() on powerpc again").
      
      Fixes: 0ebeea8c ("bpf: Restrict bpf_probe_read{, str}() only to archs where they work")
      Signed-off-by: NTiezhu Yang <yangtiezhu@loongson.cn>
      Signed-off-by: NThomas Bogendoerfer <tsbogend@alpha.franken.de>
      66633abd
  2. 14 3月, 2021 1 次提交
    • H
      MIPS: clean up CONFIG_MIPS_PGD_C0_CONTEXT handling · c6972fb9
      Huang Pei 提交于
      +. LOONGSON64 use 0x98xx_xxxx_xxxx_xxxx as xphys cached, instread of
      0xa8xx_xxxx_xxxx_xxxx
      
      +. let CONFIG_MIPS_PGD_C0_CONTEXT depend on 64bit
      
      +. cast CAC_BASE into u64 to silence warning on MIPS32
      
      CP0 Context has enough room for wraping pgd into its 41-bit PTEBase field.
      
      +. For XPHYS, the trick is that pgd is 4kB aligned, and the PABITS <= 53,
      only save 53 - 12 = 41 bits, aka :
      
         bit[63:59] | 0000 00 |  bit[53:12] | 0000 0000 0000
      
      +. for CKSEG0, only save 29 - 12 = 17 bits
      
      when switching pgd, only need to save bit[53:12] or bit[28:12] into
      CP0 Context's bit[63:23], see folling asm generated at run time
      
      tlbmiss_handler_setup_pgd:
      	.set	push
      	.set	noreorder
      
      	dsra	a2, a0, 29
      	move	a3, a0
      	dins	a0, zero, 29, 35
      	daddiu	a2, a2, 4	//for CKSEG0, a2 from 0xfffffffffffffffc
      				//into 0
      
      	movn	a0, a3, a2
      	dsll	a0, a0, 11
      	jr	ra
      	dmtc0	a0, CP0_CONTEXT
      
      	.set	pop
      
      when using it on page walking
      
      	dmfc0	k0, CP0_CONTEXT
      	dins	k0, zero, 0, 23	         // zero badv2
      	ori	k0, k0, (CAC_BASE >> 53) // *prefix* with bit[63:59]
      	drotr	k0, k0, 11		 // kick it in the right place
      Signed-off-by: NHuang Pei <huangpei@loongson.cn>
      Signed-off-by: NThomas Bogendoerfer <tsbogend@alpha.franken.de>
      c6972fb9
  3. 10 3月, 2021 1 次提交
  4. 06 3月, 2021 3 次提交
  5. 13 2月, 2021 3 次提交
  6. 05 2月, 2021 2 次提交
  7. 22 1月, 2021 5 次提交
  8. 15 1月, 2021 1 次提交
  9. 06 1月, 2021 3 次提交
    • A
      Kconfig: regularize selection of CONFIG_BINFMT_ELF · 41026c34
      Al Viro 提交于
      with mips converted to use of fs/config_binfmt_elf.c, there's no
      need to keep selects of that thing all over arch/* - we can simply
      turn into def_bool y if COMPAT && BINFMT_ELF (in fs/Kconfig.binfmt)
      and get rid of all selects.
      
      Several architectures got those selects wrong (e.g. you could
      end up with sparc64 sans BINFMT_ELF, with select violating
      dependencies, etc.)
      
      Randy Dunlap has spotted some of those; IMO this is simpler than
      his fix, but it depends upon the stuff that would need to be
      backported, so we might end up using his variant for -stable.
      Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>
      41026c34
    • A
      mips compat: switch to compat_binfmt_elf.c · 0bb87f05
      Al Viro 提交于
      Like amd64, mips has two 32bit ABIs - o32 and n32.  Unlike amd64,
      it does not use compat_binfmt_elf.c for either of those; each
      of those ABIs has a binfmt handler of its own, both very similar
      to fs/compat_binfmt_elf.c.  And the same technics as we use on
      amd64 can be used to make fs/compat_binfmt_elf.c handle both.
      	* merge elfo32_check_arch() with elfn32_check_arch(),
      make that serve as compat_elf_check_arch().  Note that
      SET_PERSONALITY2() is already the same for all ABI variants -
      it looks at the elf header to choose the flags to set.
      	* add asm/elfcore-compat.h, using the bigger (n32) variant
      of elf32_prstatus as compat_elf_prstatus there.
      	* make PRSTATUS_SIZE() and SET_PR_FPVALID() choose the
      right layout, same as done for amd64.  test_thread_flag(TIF_32BIT_REGS)
      is used as the predicate.
      
      Voila - we are rid of binfmt_elf{n,o}32.c; fs/compat_binfmt_elf.c is
      used, same as for all other ELF-supporting 64bit architectures that
      need 32bit compat.
      Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>
      0bb87f05
    • A
      mips: KVM_GUEST makes no sense for 64bit builds... · fd624c71
      Al Viro 提交于
      it's always been about MIPS32
      Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>
      fd624c71
  10. 04 1月, 2021 2 次提交
  11. 14 12月, 2020 1 次提交
  12. 04 12月, 2020 2 次提交
    • W
      MIPS: SMP-CPS: Add support for irq migration when CPU offline · d8d3276b
      Wei Li 提交于
      Currently we won't migrate irqs when offline CPUs, which has been
      implemented on most architectures. That will lead to some devices work
      incorrectly if the bound cores are offline.
      
      While that can be easily supported by enabling GENERIC_IRQ_MIGRATION.
      But i don't pretty known the reason it was not supported on all MIPS
      platforms.
      
      This patch add the support for irq migration on MIPS CPS platform, and
      it's tested on the interAptiv processor.
      Signed-off-by: NWei Li <liwei391@huawei.com>
      Signed-off-by: NThomas Bogendoerfer <tsbogend@alpha.franken.de>
      d8d3276b
    • X
      MIPS: Enable GCOV · 8b3165e5
      Xingxing Su 提交于
      Enable gcov profiling of the entire kernel on mips. Required changes
      include disabling profiling for:
      
      * arch/kernel/boot/compressed: not linked to main kernel.
      
      Lightly tested on Loongson 3A3000 an 3A4000, seems to work as expected.
      
      without "GCOV_PROFILE := n" in compressed Makefile,
      build errors as follows:
      ...
      ld: arch/mips/boot/compressed/string.o:(.data+0x88):
       undefined reference to `__gcov_merge_add'
      ld: arch/mips/boot/compressed/string.o:
       in function `_GLOBAL__sub_I_00100_0_memcpy':
      string.c:(.text.startup+0x4): undefined reference to `__gcov_init'
      ld: arch/mips/boot/compressed/string.o:
       in function `_GLOBAL__sub_D_00100_1_memcpy':
      string.c:(.text.exit+0x0): undefined reference to `__gcov_exit'
      ...
      Signed-off-by: NYouling Tang <tangyouling@loongson.cn>
      Signed-off-by: NXingxing Su <suxingxing@loongson.cn>
      Signed-off-by: NThomas Bogendoerfer <tsbogend@alpha.franken.de>
      8b3165e5
  13. 27 11月, 2020 1 次提交
    • J
      MIPS: Loongson64: Add KASLR support · a307a4ce
      Jinyang He 提交于
      Provide a weak plat_get_fdt() in relocate.c in case some platform enable
      USE_OF while plat_get_fdt() is useless.
      
      1MB RELOCATION_TABLE_SIZE is small for Loongson64 because too many
      instructions should be relocated. 2MB is enough in present.
      
      Add KASLR support for Loongson64.
      
      KASLR(kernel address space layout randomization)
      
      To enable KASLR on Loongson64:
      First, make loongson3_defconfig.
      Then, enable CONFIG_RELOCATABLE and CONFIG_RANDOMIZE_BASE.
      Finally, compile the kernel.
      
      To test KASLR on Loongson64:
      Start machine with KASLR kernel.
      
      The first time:
      # cat /proc/iomem
      00200000-0effffff : System RAM
        02f30000-03895e9f : Kernel code
        03895ea0-03bc7fff : Kernel data
        03e30000-04f43f7f : Kernel bss
      
      The second time:
      # cat /proc/iomem
      00200000-0effffff : System RAM
        022f0000-02c55e9f : Kernel code
        02c55ea0-02f87fff : Kernel data
        031f0000-04303f7f : Kernel bss
      
      We see that code, data and bss sections become randomize.
      Signed-off-by: NJinyang He <hejinyang@loongson.cn>
      Signed-off-by: NThomas Bogendoerfer <tsbogend@alpha.franken.de>
      a307a4ce
  14. 18 11月, 2020 1 次提交
  15. 07 11月, 2020 1 次提交
  16. 06 11月, 2020 1 次提交
  17. 31 10月, 2020 1 次提交
    • A
      timekeeping: default GENERIC_CLOCKEVENTS to enabled · 0774a6ed
      Arnd Bergmann 提交于
      Almost all machines use GENERIC_CLOCKEVENTS, so it feels wrong to
      require each one to select that symbol manually.
      
      Instead, enable it whenever CONFIG_LEGACY_TIMER_TICK is disabled as
      a simplification. It should be possible to select both
      GENERIC_CLOCKEVENTS and LEGACY_TIMER_TICK from an architecture now
      and decide at runtime between the two.
      
      For the clockevents arch-support.txt file, this means that additional
      architectures are marked as TODO when they have at least one machine
      that still uses LEGACY_TIMER_TICK, rather than being marked 'ok' when
      at least one machine has been converted. This means that both m68k and
      arm (for riscpc) revert to TODO.
      
      At this point, we could just always enable CONFIG_GENERIC_CLOCKEVENTS
      rather than leaving it off when not needed. I built an m68k
      defconfig kernel (using gcc-10.1.0) and found that this would add
      around 5.5KB in kernel image size:
      
         text	   data	    bss	    dec	    hex	filename
      3861936	1092236	 196656	5150828	 4e986c	obj-m68k/vmlinux-no-clockevent
      3866201	1093832	 196184	5156217	 4ead79	obj-m68k/vmlinux-clockevent
      
      On Arm (MACH_RPC), that difference appears to be twice as large,
      around 11KB on top of an 6MB vmlinux.
      Reviewed-by: NGeert Uytterhoeven <geert@linux-m68k.org>
      Acked-by: NGeert Uytterhoeven <geert@linux-m68k.org>
      Tested-by: NGeert Uytterhoeven <geert@linux-m68k.org>
      Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      0774a6ed
  18. 13 10月, 2020 2 次提交
  19. 12 10月, 2020 1 次提交
    • T
      MIPS: Loongson64: Select SMP in Kconfig to avoid build error · 1062fc45
      Tiezhu Yang 提交于
      In the current code, CONFIG_SMP can be set as N by user on the Loongson
      platform, then there exists the following build error under !CONFIG_SMP:
      
        CC      arch/mips/kernel/asm-offsets.s
      In file included from ./include/linux/gfp.h:9:0,
                       from ./include/linux/xarray.h:14,
                       from ./include/linux/radix-tree.h:18,
                       from ./include/linux/fs.h:15,
                       from ./include/linux/compat.h:17,
                       from arch/mips/kernel/asm-offsets.c:12:
      ./include/linux/topology.h: In function 'numa_node_id':
      ./include/linux/topology.h:119:2: error: implicit declaration of function 'cpu_logical_map' [-Werror=implicit-function-declaration]
        return cpu_to_node(raw_smp_processor_id());
        ^
      cc1: some warnings being treated as errors
      scripts/Makefile.build:117: recipe for target 'arch/mips/kernel/asm-offsets.s' failed
      make[1]: *** [arch/mips/kernel/asm-offsets.s] Error 1
      
      Select SMP in Kconfig to avoid the above build error and then remove
      CONFIG_SMP=y in loongson3_defconfig.
      Signed-off-by: NTiezhu Yang <yangtiezhu@loongson.cn>
      Signed-off-by: NThomas Bogendoerfer <tsbogend@alpha.franken.de>
      1062fc45
  20. 09 10月, 2020 1 次提交
  21. 28 9月, 2020 1 次提交
  22. 27 9月, 2020 1 次提交
  23. 25 9月, 2020 1 次提交
  24. 18 9月, 2020 3 次提交