1. 05 3月, 2011 1 次提交
    • B
      sfc: Use write-combining to reduce TX latency · 65f0b417
      Ben Hutchings 提交于
      Based on work by Neil Turton <nturton@solarflare.com> and
      Kieran Mansley <kmansley@solarflare.com>.
      
      The BIU has now been verified to handle 3- and 4-dword writes within a
      single 128-bit register correctly.  This means we can enable write-
      combining and only insert write barriers between writes to distinct
      registers.
      
      This has been observed to save about 0.5 us when pushing a TX
      descriptor to an empty TX queue.
      Signed-off-by: NBen Hutchings <bhutchings@solarflare.com>
      65f0b417
  2. 01 3月, 2011 8 次提交
  3. 28 2月, 2011 8 次提交
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  6. 25 2月, 2011 8 次提交