The RK808 and RK805 PMICs are using a similar register map.
We can reuse the clk driver for the RK805 PMIC. So let's add
the RK805 in the Kconfig description.
Signed-off-by: NElaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: NJoseph Chen <chenjh@rock-chips.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

HSDK board manages its clocks using various PLLs. These PLL have same
dividers and corresponding control registers mapped to different addresses.
So we add one common driver for such PLLs.

Each PLL on HSDK board consists of three dividers: IDIV, FBDIV and
ODIV. Output clock value is managed using these dividers.

We add pre-defined tables with supported rate values and appropriate
configurations of IDIV, FBDIV and ODIV for each value.

As of today we add support for PLLs that generate clock for the
HSDK arc cpus, system, ddr, AXI tunnel and hdmi.

By this patch we add support for several plls (arc cpus pll and others),
so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll
and regular probing for others plls.
Signed-off-by: NEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: NVineet Gupta <vgupta@synopsys.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Update IDT VersaClock 5 driver to support IDT VersaClock 6 5P49V6901.
This chip has two clock inputs (external XTAL or external CLKIN), four
fractional dividers (FODs) and five clock outputs (four universal clock
outputs and one reference clock output at OUT0_SELB_I2C).
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alexey Firago <alexey_firago@mentor.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: linux-renesas-soc@vger.kernel.org
Tested-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
on Salvator-XS with the display LVDS output.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add a driver for the clocks provided by the MIPS Boston board from
Imagination Technologies. 2 clocks are provided - the system clock & the
CPU clock - and each is a simple fixed rate clock whose frequency can be
determined by reading a register provided by the board.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>
Reviewed-by: NJames Hogan <james.hogan@imgtec.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: linux-clk@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16483/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

The Cortina Systems Gemini (SL3516/CS3516) has an on-chip clock
controller that derive all clocks from a single crystal, using some
documented and some undocumented PLLs, half dividers, counters and
gates. This is a best attempt to construct a clock driver for the
clocks so at least we can gate off unused hardware and driver the
PCI bus clock.
Acked-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
[sboyd@codeaurora.org: Fix devm_ioremap_resource() return value
checking]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

In K2G, the clock handling is done through firmware executing on a
separate core. Linux kernel needs to communicate to the firmware
through TI system control interface to access any power management
related resources, including clocks.

The keystone sci-clk driver does this, by communicating to the
firmware through the TI SCI driver. The driver adds support for
registering clocks through DT, and basic required clock operations
like prepare/get_rate, etc.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
[sboyd@codeaurora.org: Make ti_sci_init_clocks() static]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The hi655x multi function device is a PMIC providing regulators.

The PMIC also provides a clock for the WiFi and the Bluetooth, let's implement
this clock in order to add it in the hi655x MFD and allow proper wireless
initialization.
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
[sboyd@codeaurora.org: Remove clkdev usage]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add driver for IDT VersaClock 5 5P49V5923 and 5P49V5933 chips. These
chips have two clock inputs, XTAL or CLK, which are muxed into single
PLL/VCO input. In case of 5P49V5923, the XTAL in built into the chip
while the 5P49V5923 requires external XTAL.

The PLL feeds two fractional dividers. Each fractional divider feeds
output mux, which allows selecting between clock from the fractional
divider itself or from output mux on output N-1. In case of output
mux 0, the output N-1 is instead connected to the output from the mux
feeding the PLL.

The driver thus far supports only the 5P49V5923 and 5P49V5933, while
it should be easily extensible to the whole 5P49V59xx family of chips
as they are all pretty similar.
Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Reviewed-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: linux-renesas-soc@vger.kernel.org
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The CDCE925 is a member of the CDCE(L)9xx programmable clock generator
family.  There are also CDCE913, CDCE937, CDCE949 which have different
number of PLLs and outputs.

The clk-cdce925 driver supports only CDCE925 in the family.  This adds
support for the CDCE913, CDCE937, CDCE949, too.
Signed-off-by: NAkinobu Mita <akinobu.mita@gmail.com>
Acked-by: NRob Herring <robh@kernel.org>
Cc: Mike Looijmans <mike.looijmans@topic.nl>
Cc: Michael Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

s2mps11 and max77686 clock drivers can be compile tested to increase
build coverage.
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This includes UniPhier clock driver code, except SoC-specific
data arrays.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add a Kconfig to define clock configuration for each SoC, and
modify the Makefile to build drivers that only selected in config.
Signed-off-by: NShunli Wang <shunli.wang@mediatek.com>
Signed-off-by: NJames Liao <jamesjj.liao@mediatek.com>
Signed-off-by: NErin Lo <erin.lo@mediatek.com>
Tested-by: NJohn Crispin <blogic@openwrt.org>
Reviewed-by: NMatthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Maxim Max77620 has one 32KHz clock output and the clock HW
IP used on this PMIC is same as what it is there in the MAX77686.

Add clock driver support for MAX77620 on the MAX77686 driver.

CC: Krzysztof Kozlowski <k.kozlowski@samsung.com>
CC: Javier Martinez Canillas <javier@dowhile0.org>
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Tested-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The clock IP used on the Maxim PMICs max77686 and max77802 are
same. The configuration of clock register is also same except
the number of clocks.

Part of common code utilisation, there is 3 files for these chips
clock driver, one for common and two files for driver registration.

Combine both drivers into single file and move common code into
same common file reduces the 2 files and make max77686 and max77802
clock driver in single fine. This driver does not depends on the
parent driver structure. The regmap handle is acquired through
regmap APIs for the register access.

This combination of driver helps on adding clock driver for different
Maxim PMICs which has similar clock IP like MAX77620 and MAX20024.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
CC: Krzysztof Kozlowski <k.kozlowski@samsung.com>
CC: Javier Martinez Canillas <javier@dowhile0.org>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Tested-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The clk-oxnas driver is specific to its architecture, so do not
propose it on other architectures, unless build-testing.
Signed-off-by: NJean Delvare <jdelvare@suse.de>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160707091844.196a7930@endymion

Start our new clock infrastructure by adding the registration code, common
structure and common code.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-3-maxime.ripard@free-electrons.com

The RK808 and RK818 PMICs are using a similar register map.
We can reuse the clk driver for the RK818 PMIC. So let's add
the RK818 in the Kconfig description.
Signed-off-by: NWadim Egorov <w.egorov@phytec.de>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1464850228-17244-4-git-send-email-w.egorov@phytec.de

Break the AmLogic clock code up so that only the necessary parts are
compiled and linked. The core code is selected by both arm and arm64
builds with COMMON_CLK_AMLOGIC. The individual drivers have their own
config options as well.
Tested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

Commit 378523d1 ("clk: add lpc18xx creg clk driver")
added a new clock driver but missed the proper MFD_SYSCON select.
Fix it.

Fixes: 378523d1 ("clk: add lpc18xx creg clk driver")
Signed-off-by: NEzequiel Garcia <ezequiel@vanguardiasur.com.ar>
Acked-by: NJoachim Eastwood <manabian@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This clock driver implements PIC32 specific clock-tree. clock-tree
entities can only be configured through device-tree file (OF).
Signed-off-by: NPurna Chandra Mandal <purna.mandal@microchip.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-clk@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13247/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add Oxford Semiconductor OXNAS SoC Family Standard Clocks support.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
[sboyd@codeaurora.org: Drop NULL/continue check in registration
loop]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Currently the decision whether to build the renesas-cpg-mssr and
clk-mstp drivers is handled by Makefile logic.  However, the rcar-sysc
driver will need to know whether CPG/MSSR and/or CPG/MSTP support are
available or not.

To avoid having to duplicate this logic, move it to Kconfig. Provide
non-visible CLK_RENESAS_CPG_MSSR and CLK_RENESAS_CPG_MSTP Kconfig
symbols, which can be used by both Makefiles and C code.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>

On dm814x we have 13 ADPLLs with 3 to 4 outputs on each. The
ADPLLs have several dividers and muxes controlled by a shared
control register for each PLL.

Note that for the clocks to work as device drivers for booting on
dm814x, this patch depends on "ARM: OMAP2+: Change core_initcall
levels to postcore_initcall" that has already been merged.

Also note that this patch does not implement clk_set_rate for the
PLL, that will be posted later on when available.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: NTero Kristo <t-kristo@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

This config was used for the ARM port so that it could use a
machine specific clkdev.h include, but those are all gone now.
The MIPS architecture is the last user, and from what I can tell
it doesn't actually use it anyway, so let's remove the config all
together.

Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: <linux-mips@linux-mips.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Reviewed-by: NJoshua Henderson <joshua.henderson@microchip.com>

There are two TI CDCE clock chips in this file. Move them close
together so they're easier to find.

No functional change, just cosmetic.
Signed-off-by: NMike Looijmans <mike.looijmans@topic.nl>
[sboyd@codeaurora.org: Alphabetize]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Simple cosmetic fix.
Signed-off-by: NMike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Move all vendor's Kconfig into CCF menu section to prevent
new drivers putting their Kconfig files in a wrong place.

Some Kconfigs need to be modified at the same time to avoid build
warnings.
Signed-off-by: NJames Liao <jamesjj.liao@mediatek.com>
Acked-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
[sboyd@codeaurora.org: Fix typos in commit message]
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Presumably the second COMMON_CLK_NXP config option in
drivers/clk/Kconfig appeared after a merge conflict resolution, remove
the wrong record of two.
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

Add support for all configurable clocks found on NXP LPC32xx SoC.

The list contains several heterogenous groups of clocks:
* system clocks including multiple dividers and muxes,
* x397 PLL, HCLK PLL and USB PLL,
* peripheral clocks inherited from rtc, hclk and pclk,
* USB controller clocks: AHB slave, I2C, OTG, OHCI and device.
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

The change adds COMMON_CLK_NXP configuration symbol and enables it for
NXP LPC18XX architecture, this is needed to reuse drivers/clk/nxp
folder for NXP common clock framework drivers other than LPC18XX one.
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>
Acked-by: NJoachim Eastwood <manabian@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

This patch adds CS2000 Fractional-N driver as clock provider.
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
[sboyd@codeaurora.org: Fix unsigned checked for < 0 in
cs2000_ratio_get()]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

LS2080A is the first implementation of the chassis 3 clockgen, which
has a different register layout than previous chips.  It is also little
endian, unlike previous chips.
Signed-off-by: NScott Wood <scottwood@freescale.com>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>

These drivers only have runtime but no build time dependencies so can be
built for testing purposes if the Kconfig COMPILE_TEST option is enabled.

This is useful to have more build coverage and make sure that drivers are
not affected by changes that could cause build regressions.
Signed-off-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Acked-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch adds the driver and devicetree documentation for the
Silicon Labs SI514 clock generator chip. This is an I2C controlled
oscillator capable of generating clock signals ranging from 100kHz
to 250MHz.
Signed-off-by: NMike Looijmans <mike.looijmans@topic.nl>
[sboyd@codeaurora.org: Drop clk.h include, remove some casts]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch converts the code to use rational best approximation algorithm which
is much more precise.
Suggested-by: NStephen Boyd <sboyd@codeaurora.org>
Reviewed-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

On some ARM based systems, a separate Cortex-M based System Control
Processor(SCP) provides the overall power, clock, reset and system
control. System Control and Power Interface(SCPI) Message Protocol
is defined for the communication between the Application Cores(AP)
and the SCP.

This patch adds support for the clocks provided by SCP using SCPI
protocol.
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Cc: Mike Turquette <mturquette@baylibre.com>
Cc: Liviu Dudau <Liviu.Dudau@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Jon Medhurst (Tixy) <tixy@linaro.org>
Cc: linux-clk@vger.kernel.org

This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only supports the following setup,
and uses a fixed setting for the output muxes:
  Y1 is derived from the input clock
  Y2 and Y3 derive from PLL1
  Y4 and Y5 derive from PLL2
Given a target output frequency, the driver will set the PLL and
divider to best approximate the desired output.
Signed-off-by: NMike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.

We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
"CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.
Signed-off-by: NJorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: NBintian Wang <bintian.wang@huawei.com>
Acked-by: NHaojian Zhuang <haojian.zhuang@linaro.org>
Reviewed-by: NZhangfei Gao <zhangfei.gao@linaro.org>
Tested-by: NWill Deacon <will.deacon@arm.com>
Tested-by: NTyler Baker <tyler.baker@linaro.org>
Tested-by: NKevin Hilman <khilman@linaro.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Having this Kconfig sourced outside the clk menu means the option
is under the "Device Drivers" menu instead of the "Common Clock
Framework" menu. Move it so that the bcm clock config options are
in the right place.

Cc: Alex Elder <elder@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The EMC clock driver uses symbols exported by the EMC driver, so it
needs the corresponding dependency to avoid build breakage.
Signed-off-by: NThierry Reding <treding@nvidia.com>