Add the clocks supported in global clock controller which clock the
peripherals like BLSPs, SDCC, USB, MDSS etc. Register all the clocks
to the clock framework for the clients to be able to request for them.
Signed-off-by: NShefali Jain <shefjain@codeaurora.org>
Signed-off-by: NTaniya Das <tdas@codeaurora.org>
Co-developed-by: NTaniya Das <tdas@codeaurora.org>
Signed-off-by: NAnu Ramanathan <anur@codeaurora.org>
[bamse, vkoul: rebase and tidyup for upstream]
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Acked-by: NRob Herring <robh@kernel.org>
[sboyd@kernel.org: Lowercase hex]
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

This is used by the QCS404 GCC driver, export it to allow that driver to
be compiled as a module..
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

The way this function is implemented caused some confusion when
converting the TI DaVinci platform to using the common clock framework.

Current kernel supports booting DaVinci boards both in device tree as
well as legacy, board-file mode. In the latter, we always end up
calling clk_get_sys() as of_node is NULL and __of_clk_get_by_name()
returns -ENOENT.

It was not obvious at first glance how clk_get(dev, NULL) will work in
board-file mode since we always call __of_clk_get_by_name(). Let's make
it clearer by checking if of_node is NULL and skipping right to
clk_get_sys().

Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: David Lechner <david@lechnology.com>
Reviewed-by: NDavid Lechner <david@lechnology.com>
Reviewed-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NBartosz Golaszewski <bgolaszewski@baylibre.com>
Signed-off-by: NRussell King <rmk+kernel@armlinux.org.uk>

PWM2 is commonly used to control voltage of PWM regulator of VDD_LOG in
RK3399. On the Firefly-RK3399 board, PWM2 outputs 40 KHz square wave
from power on and the VDD_LOG is about 0.9V. When the kernel boots
normally into the system, the PWM2 keeps outputing PWM signal.

But the kernel hangs randomly after "Starting kernel ..." line on that
board. When it happens, PWM2 outputs high level which causes VDD_LOG
drops to 0.4V below the normal operating voltage.

By adding "pclk_rkpwm_pmu" to the rk3399_pmucru_critical_clocks array,
PWM clock is ensured to be prepared at startup and the PWM2 output is
normal. After repeated tests, the early boot hang is gone.

This patch works on both Firefly-RK3399 and ROC-RK3399-PC boards.
Signed-off-by: NLevin Du <djw@t-chip.com.cn>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

This fix rounds the clock rate properly by using quotient and not
remainder in the calculation. This issue was found while testing HDMI
in the Juno platform.

Fixes: 6d6a1d82 ("clk: add support for clocks provided by SCMI")
Acked-by: NSudeep Holla <sudeep.holla@arm.com>
Signed-off-by: NAmit Daniel Kachhap <amit.kachhap@arm.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add support for the display clock controller found on SDM845
based devices. This would allow display drivers to probe and
control their clocks.
Signed-off-by: NTaniya Das <tdas@codeaurora.org>
[sboyd@kernel.org: Remove CLK_GET_RATE_NOCACHE everywhere]
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

When building armada-37xx-periph, num_parents isn't used in function
clk_pm_cpu_get_parent:
drivers/clk/mvebu/armada-37xx-periph.c: In function ‘clk_pm_cpu_get_parent’:
drivers/clk/mvebu/armada-37xx-periph.c:419:6: warning: unused variable ‘num_parents’ [-Wunused-variable]
  int num_parents = clk_hw_get_num_parents(hw);
      ^~~~~~~~~~~
Remove the declaration of num_parents to dispose the warning.

Fixes: 616bf80d ("clk: mvebu: armada-37xx-periph: Fix wrong return value in get_parent")
Signed-off-by: NAnders Roxell <anders.roxell@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Remove unused 'mout_user_aclk400_mcuisp_p4x12' variable to fix GCC warning:

    drivers/clk/samsung/clk-exynos4412-isp.c:40:27: warning:
        'mout_user_aclk400_mcuisp_p4x12' defined but not used [-Wunused-const-variable=]
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add Actions Semi S700 SoC clock support
Signed-off-by: NParthiban Nallathambi <pn@denx.de>
Signed-off-by: NSaravanan Sekar <sravanhome@gmail.com>
Reviewed-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add REGMAP_MMIO as dependency to avoid undefined
reference to regmap symbols.

Fixes: d85d2005 ("clk: actions: Add S900 SoC clock support")
Signed-off-by: NSaravanan Sekar <sravanhome@gmail.com>
Reviewed-by: NAndreas Färber <afaerber@suse.de>
Reviewed-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add clock control for SPI controller on UniPhier SoCs.
Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add USB3 PHY clocks where missing.  Use fixed-factor clocks for those
without gating.

For clarification, prefix clock names with 'ss' or 'hs'.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

The Denali NAND controller IP needs three clocks:

 - clk: controller core clock

 - clk_x: bus interface clock

 - ecc_clk: clock at which ECC circuitry is run

Currently, only the first one (50MHz) is provided.  The rest of the
two clock ports must be connected to the 200MHz clock line.  Add this.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

These clocks have low jitter paths to certain parents. To model these
correctly, use the sdmmc mux divider clock type.
Signed-off-by: NPeter De-Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NAapo Vienamo <avienamo@nvidia.com>
Acked-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add a clock type to model the sdmmc switch divider clocks which have paths
to source clocks bypassing the divider (Low Jitter paths). These
are handled by selecting the lj path when the divider is 1 (ie the
rate is the parent rate), otherwise the normal path with divider
will be selected. Otherwise this clock behaves as a normal peripheral
clock.
Signed-off-by: NPeter De-Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NAapo Vienamo <avienamo@nvidia.com>
Acked-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Move this to a separate file so it can be used to calculate the sdmmc
clock dividers.
Signed-off-by: NPeter De-Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: NAapo Vienamo <avienamo@nvidia.com>
Acked-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Add the missing linux/delay.h include statement for udelay() used by
fence_udelay() macro.
Signed-off-by: NAapo Vienamo <avienamo@nvidia.com>
Acked-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

of_find_compatible_node() is returning a device node with refcount
incremented and must be explicitly decremented after the last use
which is right after the us in of_iomap() here.
Signed-off-by: NNicholas Mc Guire <hofrat@osadl.org>
Fixes: 4a5f720b ("clk: imx: add clock driver for imx6sll")
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

of_find_compatible_node() is returning a device node with refcount
incremented and must be explicitly decremented after the last use
which is right after the us in of_iomap() here.
Signed-off-by: NNicholas Mc Guire <hofrat@osadl.org>
Fixes: 787b4271 ("clk: imx: add imx6ul clk tree support")
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

i.MX6SX has a 16KB always-on ocram bank called
ocram_s, and its clock gate in CCM CCGR1 CG14
needs to be enabled before access, add it to
clock tree.
Signed-off-by: NAnson Huang <Anson.Huang@nxp.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

The return value of the get_parent operation is a u8, whereas a -EINVAL
was returned. This wrong value was return if the value was bigger that
the number of parent but this case was already handled by the core.

So we can just remove this chunk of code to fix the issue.
Reported-by: NDan Carpenter <dan.carpenter@oracle.com>
Fixes: 9818a7a4 ("clk: mvebu: armada-37xx-periph: prepare cpu clk to
be used with DVFS")
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Fixed factor clock has two initializations at of_clk_init() time
and during platform driver probe. Before of_clk_init() call,
node is marked as populated and so its probe never gets called.

During of_clk_init() fixed factor clock registration may fail if
any of its parent clock is not registered. In this case, it doesn't
get chance to retry registration from probe. Clear OF_POPULATED
flag if fixed factor clock registration fails so that clock
registration is attempted again from probe.
Signed-off-by: NRajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Patch "clk: core: Copy connection id" made it so that the connector id
'con_id' is kstrdup_const()ed to cater to drivers that pass non-constant
connection ids. The patch added the corresponding kfree_const to
__clk_free_clk(), but struct clk's can be freed also via __clk_put().
Add the kfree_const call to __clk_put() and add comments to both
functions to remind that the logic in them should be kept in sync.

Fixes: 253160a8 ("clk: core: Copy connection id")
Signed-off-by: NMikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: NLeonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

SPDX headers updated for common/branch/pll/regmap files.
Signed-off-by: NTaniya Das <tdas@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

The Exynos5440 is not actively developed, there are no development
boards available and probably there are no real products with it.
Remove wide-tree support for Exynos5440.
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: NChanwoo Choi <cw00.choi@samsung.com>
Acked-by: NStephen Boyd <sboyd@kernel.org>
Acked-by: NSylwester Nawrocki <snawrocki@kernel.org>

Add the RPMh clock driver to control the RPMh managed clock resources on
some of the Qualcomm Technologies, Inc. SoCs.
Signed-off-by: NTaniya Das <tdas@codeaurora.org>
[sboyd@kernel.org: Clean up whitespace, indentation, remove
cmd_db_ready check]
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

The HPLL can be configured through a register (SCU24), however some
platforms chose to configure it through the strapping settings and do
not use the register. This was not noticed as the logic for bit 18 in
SCU24 was confused: set means programmed, but the driver read it as set
means strapped.

This gives us the correct HPLL value on Palmetto systems, from which
most of the peripheral clocks are generated.

Fixes: 5eda5d79 ("clk: Add clock driver for ASPEED BMC SoCs")
Cc: stable@vger.kernel.org # v4.15
Reviewed-by: NCédric Le Goater <clg@kaod.org>
Signed-off-by: NJoel Stanley <joel@jms.id.au>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

__of_clk_get() calls of_parse_phandle_with_args(), which rejects
negative indices since commit bd69f73f ("of: Create function for
counting number of phandles in a property").
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: NStephen Boyd <sboyd@kernel.org>
Signed-off-by: NRussell King <rmk+kernel@armlinux.org.uk>

Add clkctrl data for the m_can clocks and register it within the
clkctrl driver
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NStephen Boyd <sboyd@kernel.org>
CC: Tero Kristo <t-kristo@ti.com>
Signed-off-by: NFaiz Abbas <faiz_abbas@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

This clock is needed for iMX mailbox driver
Signed-off-by: NOleksij Rempel <o.rempel@pengutronix.de>
Reviewed-by: NDong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Adopt the SPDX license identifier headers to ease license compliance
management.
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

Switching the CPU from the L2 or L3 frequencies (300 and 200 Mhz
respectively) to L0 frequency (1.2 Ghz) requires a significant amount
of time to let VDD stabilize to the appropriate voltage. This amount of
time is large enough that it cannot be covered by the hardware
countdown register. Due to this, the CPU might start operating at L0
before the voltage is stabilized, leading to CPU stalls.

To work around this problem, we prevent switching directly from the
L2/L3 frequencies to the L0 frequency, and instead switch to the L1
frequency in-between. The sequence therefore becomes:

1. First switch from L2/L3(200/300MHz) to L1(600MHZ)
2. Sleep 20ms for stabling VDD voltage
3. Then switch from L1(600MHZ) to L0(1200Mhz).

It is based on the work done by Ken Ma <make@marvell.com>

Cc: stable@vger.kernel.org
Fixes: 2089dc33 ("clk: mvebu: armada-37xx-periph: add DVFS support for cpu clocks")
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: NStephen Boyd <sboyd@kernel.org>

GEN_CLK is able to route several internal clocks to one of the SoC
pads. In the future, even more clocks could be made accessible using
cts_msr_clk - the clock measure block.
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>

HHI_GEN_CLK_CTNL is defined twice, just remove the duplicate definition

Fixes: 738f66d3 ("clk: gxbb: add AmLogic GXBB clk controller driver")
Acked-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>

Adding clocks for the pcie driver. Due to the ASIC design,
the pcie controller re-use part of the mipi clock logic,
so the mipi clock is also added.
Tested-by: NJianxin Qin <jianxin.qin@amlogic.com>
Signed-off-by: NYixun Lan <yixun.lan@amlogic.com>
[amended to remove unnecessary locales]
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>

clk-audio-divider is no longer used, we can remove it.
Acked-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>

It is actually a lot easier to setup the PLL with carefully chosen rates
than relying on CCF clock propagation for this audio use case.
This way, we can make sure we will always be able to provide the common
audio clock rates, while having the PLL in the optimal operating range.

For this, we stop the rate propagation at the mux picking the
PLL and let it round to the closest matching PLL.

Doing so, we can use the generic divider for the i2s clock.
clk-audio-divider is no longer required. It was a (poor) attempt
to use CCF rate propagation while making sure the PLL rate would
be high enough to work with audio use cases.
Acked-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>

The axg audio clock controller is the clock generation unit for the
amlogic audio subsystem of A113 based SoCs. It may be clocked by 8
different plls provided by the primary clock controller and also by
10 slave bit clocks and 10 slave sample clocks which may be provided
by external components, such as audio codecs, through the SoC pads.

It contains several muxes, dividers and gates which are fed into the
the different devices of the audio subsystem.
Acked-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>

Add a driver to control the clock divider found in the sample clock
generator of the axg audio clock controller.

The sclk divider accumulates specific features which make the generic
divider unsuitable to control it:
- zero based divider (div = val + 1), but zero value gates the clock,
  so minimum divider value is 2.
- lrclk variant may adjust the duty cycle depending the divider value
  and the 'hi' value.
Acked-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>