1. 23 11月, 2019 3 次提交
  2. 21 11月, 2019 3 次提交
    • R
      cxgb4: add TC-MATCHALL classifier ingress offload · 21c4c60b
      Rahul Lakkireddy 提交于
      Add TC-MATCHALL classifier ingress offload support. The same actions
      supported by existing TC-FLOWER offload can be applied to all incoming
      traffic on the underlying interface.
      
      Ensure the rule priority doesn't conflict with existing rules in the
      TCAM. Only 1 ingress matchall rule can be active at a time on the
      underlying interface.
      
      v5:
      - No change.
      
      v4:
      - Added check to ensure the matchall rule's prio doesn't conflict with
        other rules in TCAM.
      - Added logic to fill default mask for VIID, if none has been
        provided, to prevent conflict with duplicate VIID rules.
      - Used existing variables in private structure to fill VIID info,
        instead of extracting the info manually.
      
      v3:
      - No change.
      
      v2:
      - Removed logic to fetch free index from end of TCAM. Must maintain
        same ordering as in kernel.
      Signed-off-by: NRahul Lakkireddy <rahul.lakkireddy@chelsio.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      21c4c60b
    • R
      cxgb4: check rule prio conflicts before offload · 41ec03e5
      Rahul Lakkireddy 提交于
      Only offload rule if it satisfies both of the following conditions:
      1. The immediate previous rule has priority <= current rule's priority.
      2. The immediate next rule has priority >= current rule's priority.
      
      Also rework free entry fetch logic to search from end of TCAM, instead
      of beginning, because higher indices have lower priority than lower
      indices. This is similar to how TC auto generates priority values.
      
      v5:
      - Fixed commit message and comment to include comparison for equal
        priority.
      
      v4:
      - Patch added in this version.
      Signed-off-by: NRahul Lakkireddy <rahul.lakkireddy@chelsio.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      41ec03e5
    • R
      cxgb4: add TC-MATCHALL classifier egress offload · 4ec4762d
      Rahul Lakkireddy 提交于
      Add TC-MATCHALL classifier offload with TC-POLICE action applied for
      all outgoing traffic on the underlying interface. Split flow block
      offload to support both egress and ingress classification.
      
      For example, to rate limit all outgoing traffic to 1 Gbps:
      
      $ tc qdisc add dev enp2s0f4 clsact
      $ tc filter add dev enp2s0f4 egress matchall skip_sw \
      	action police rate 1Gbit burst 8Kbit
      
      Note that skip_sw is important. Otherwise, both stack and hardware
      will end up doing policing. Policing can't be shared across flow
      blocks. Only 1 egress matchall rule can be active at a time on the
      underlying interface.
      
      v5:
      - No change.
      
      v4:
      - Removed check to reject police offload if prio is not 1.
      - Moved TC_SETUP_BLOCK code to separate function.
      
      v3:
      - Added check to reject police offload if prio is not 1.
      - Assign block_shared variable only for TC_SETUP_BLOCK.
      
      v2:
      - Added check to reject flow block sharing for policers.
      Signed-off-by: NRahul Lakkireddy <rahul.lakkireddy@chelsio.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      4ec4762d
  3. 20 11月, 2019 1 次提交
  4. 14 11月, 2019 1 次提交
  5. 13 11月, 2019 1 次提交
  6. 12 11月, 2019 1 次提交
  7. 09 11月, 2019 2 次提交
  8. 08 11月, 2019 6 次提交
  9. 06 11月, 2019 1 次提交
  10. 01 11月, 2019 1 次提交
  11. 31 10月, 2019 1 次提交
  12. 26 10月, 2019 1 次提交
    • R
      cxgb4: request the TX CIDX updates to status page · 7c3bebc3
      Raju Rangoju 提交于
      For adapters which support the SGE Doorbell Queue Timer facility,
      we configured the Ethernet TX Queues to send CIDX Updates to the
      Associated Ethernet RX Response Queue with CPL_SGE_EGR_UPDATE
      messages to allow us to respond more quickly to the CIDX Updates.
      But, this was adding load to PCIe Link RX bandwidth and,
      potentially, resulting in higher CPU Interrupt load.
      
      This patch requests the HW to deliver the CIDX updates to the TX
      queue status page rather than generating an ingress queue message
      (as an interrupt). With this patch, the load on RX bandwidth is
      reduced and a substantial improvement in BW is noticed at lower
      IO sizes.
      
      Fixes: d429005f ("cxgb4/cxgb4vf: Add support for SGE doorbell queue timer")
      Signed-off-by: NRaju Rangoju <rajur@chelsio.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      7c3bebc3
  13. 05 10月, 2019 1 次提交
  14. 27 9月, 2019 1 次提交
  15. 12 9月, 2019 1 次提交
  16. 15 8月, 2019 1 次提交
  17. 11 8月, 2019 1 次提交
  18. 09 8月, 2019 2 次提交
  19. 07 8月, 2019 1 次提交
  20. 31 7月, 2019 1 次提交
  21. 23 7月, 2019 1 次提交
  22. 22 7月, 2019 3 次提交
  23. 16 7月, 2019 1 次提交
  24. 13 7月, 2019 1 次提交
    • A
      cxgb4: reduce kernel stack usage in cudbg_collect_mem_region() · 752c2ea2
      Arnd Bergmann 提交于
      The cudbg_collect_mem_region() and cudbg_read_fw_mem() both use several
      hundred kilobytes of kernel stack space. One gets inlined into the other,
      which causes the stack usage to be combined beyond the warning limit
      when building with clang:
      
      drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c:1057:12: error: stack frame size of 1244 bytes in function 'cudbg_collect_mem_region' [-Werror,-Wframe-larger-than=]
      
      Restructuring cudbg_collect_mem_region() lets clang do the same
      optimization that gcc does and reuse the stack slots as it can
      see that the large variables are never used together.
      
      A better fix might be to avoid using cudbg_meminfo on the stack
      altogether, but that requires a larger rewrite.
      
      Fixes: a1c69520 ("cxgb4: collect MC memory dump")
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      752c2ea2
  25. 10 7月, 2019 3 次提交