1. 16 6月, 2016 25 次提交
    • Y
      kvm: vmx: hook preemption timer support · 64672c95
      Yunhong Jiang 提交于
      Hook the VMX preemption timer to the "hv timer" functionality added
      by the previous patch.  This includes: checking if the feature is
      supported, if the feature is broken on the CPU, the hooks to
      setup/clean the VMX preemption timer, arming the timer on vmentry
      and handling the vmexit.
      
      A module parameter states if the VMX preemption timer should be
      utilized.
      Signed-off-by: NYunhong Jiang <yunhong.jiang@intel.com>
      [Move hv_deadline_tsc to struct vcpu_vmx, use -1 as the "unset" value.
       Put all VMX bits here.  Enable it by default #yolo. - Paolo]
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      64672c95
    • Y
      kvm: vmx: rename vmx_pre/post_block to pi_pre/post_block · bc22512b
      Yunhong Jiang 提交于
      Prepare to switch from preemption timer to hrtimer in the
      vmx_pre/post_block. Current functions are only for posted interrupt,
      rename them accordingly.
      Signed-off-by: NYunhong Jiang <yunhong.jiang@intel.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      bc22512b
    • Y
      KVM: x86: support using the vmx preemption timer for tsc deadline timer · ce7a058a
      Yunhong Jiang 提交于
      The VMX preemption timer can be used to virtualize the TSC deadline timer.
      The VMX preemption timer is armed when the vCPU is running, and a VMExit
      will happen if the virtual TSC deadline timer expires.
      
      When the vCPU thread is blocked because of HLT, KVM will switch to use
      an hrtimer, and then go back to the VMX preemption timer when the vCPU
      thread is unblocked.
      
      This solution avoids the complex OS's hrtimer system, and the host
      timer interrupt handling cost, replacing them with a little math
      (for guest->host TSC and host TSC->preemption timer conversion)
      and a cheaper VMexit.  This benefits latency for isolated pCPUs.
      
      [A word about performance... Yunhong reported a 30% reduction in average
       latency from cyclictest.  I made a similar test with tscdeadline_latency
       from kvm-unit-tests, and measured
      
       - ~20 clock cycles loss (out of ~3200, so less than 1% but still
         statistically significant) in the worst case where the test halts
         just after programming the TSC deadline timer
      
       - ~800 clock cycles gain (25% reduction in latency) in the best case
         where the test busy waits.
      
       I removed the VMX bits from Yunhong's patch, to concentrate them in the
       next patch - Paolo]
      Signed-off-by: NYunhong Jiang <yunhong.jiang@intel.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      ce7a058a
    • Y
      kvm: lapic: separate start_sw_tscdeadline from start_apic_timer · 53f9eedf
      Yunhong Jiang 提交于
      The function to start the tsc deadline timer virtualization will be used
      also by the pre_block hook when we use the preemption timer; change it
      to a separate function. No logic changes.
      Signed-off-by: NYunhong Jiang <yunhong.jiang@intel.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      53f9eedf
    • P
      KVM: s390: use kvm->created_vcpus · a03825bb
      Paolo Bonzini 提交于
      The new created_vcpus field avoids possible races between enabling
      capabilities and creating VCPUs.
      Acked-by: NChristian Borntraeger <borntraeger@de.ibm.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      a03825bb
    • P
      KVM: remove kvm_vcpu_compatible · 557abc40
      Paolo Bonzini 提交于
      The new created_vcpus field makes it possible to avoid the race between
      irqchip and VCPU creation in a much nicer way; just check under kvm->lock
      whether a VCPU has already been created.
      
      We can then remove KVM_APIC_ARCHITECTURE too, because at this point the
      symbol is only governing the default definition of kvm_vcpu_compatible.
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      557abc40
    • P
      KVM: introduce kvm->created_vcpus · 6c7caebc
      Paolo Bonzini 提交于
      The race between creating the irqchip and the first VCPU is
      currently fixed by checking the presence of an irqchip before
      updating kvm->online_vcpus, and undoing the whole VCPU creation
      if someone created the irqchip in the meanwhile.
      
      Instead, introduce a new field in struct kvm that will count VCPUs
      under a mutex, without the atomic access and memory ordering that we
      need elsewhere to protect the vcpus array.  This also plugs the race
      and is more easily applicable in all similar circumstances.
      Reviewed-by: NCornelia Huck <cornelia.huck@de.ibm.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      6c7caebc
    • B
      x86/kvm/svm: Simplify cpu_has_svm() · 682a8108
      Borislav Petkov 提交于
      Use already cached CPUID information instead of querying CPUID again.
      
      No functionality change.
      Signed-off-by: NBorislav Petkov <bp@suse.de>
      Cc: Joerg Roedel <joro@8bytes.org>
      Cc: kvm@vger.kernel.org
      Cc: x86@kernel.org
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      682a8108
    • J
      MIPS: KVM: Use mipsregs.h defs for config registers · 4e10b764
      James Hogan 提交于
      Convert MIPS KVM guest register state initialisation to use the standard
      <asm/mipsregs.h> register field definitions for Config registers, and
      drop the custom definitions in kvm_host.h which it was using before.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      4e10b764
    • J
      MIPS: KVM: Report more accurate CP0_Config fields to guest · e342925f
      James Hogan 提交于
      Initialise the guest's CP0_Config register with a few more bits of
      information from the host. The BE bit should be set on big endian
      machines, the VI bit should be set on machines with a virtually tagged
      instruction cache, and the reported architecture revision should match
      that of the host (since we won't support emulating pre-r6 instruction
      encodings on r6 or vice versa).
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      e342925f
    • J
      MIPS: Add define for Config.VI (virtual icache) bit · 4b34bca0
      James Hogan 提交于
      The Config.VI bit specifies that the instruction cache is virtually
      tagged, which is checked in c-r4k.c's probe_pcache(). Add a proper
      definition for it in mipsregs.h and make use of it.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Acked-by: NRalf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      4b34bca0
    • J
      MIPS: KVM: Use host CCA for TLB mappings · 7414d2f6
      James Hogan 提交于
      KVM TLB mappings for the guest were being created with a cache coherency
      attribute (CCA) of 3, which is cached incoherent. Create them instead
      with the default host CCA, which should be the correct one for coherency
      on SMP systems.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      7414d2f6
    • J
      MIPS: KVM: Move commpage so 0x0 is unmapped · 42aa12e7
      James Hogan 提交于
      The comm page which is mapped into the guest kernel address space at
      0x0 has the unfortunate side effect of allowing guest kernel NULL
      pointer dereferences to succeed. The only constraint on this address is
      that it must be within 32KiB of 0x0, so that single lw/sw instructions
      (which have 16-bit signed offset fields) can be used to access it, using
      the zero register as a base.
      
      So lets move the comm page as high as possible within that constraint so
      that 0x0 can be left unmapped, at least for page sizes < 32KiB.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      42aa12e7
    • J
      MIPS: KVM: Add KScratch registers · 05108709
      James Hogan 提交于
      Allow up to 6 KVM guest KScratch registers to be enabled and accessed
      via the KVM guest register API and from the guest itself (the fallback
      reading and writing of commpage registers is sufficient for KScratch
      registers to work as expected).
      
      User mode can expose the registers by setting the appropriate bits of
      the guest Config4.KScrExist field. KScratch registers that aren't usable
      won't be writeable via the KVM Ioctl API.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      05108709
    • J
      MIPS: KVM: Emulate RDHWR CPUNum register · cf1fb0f2
      James Hogan 提交于
      Actually provide the VCPU number when emulating the RDHWR CPUNum
      register, so that it will match the CPUNum field of CP0_EBase register,
      rather than always returning 0.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      cf1fb0f2
    • J
      MIPS: KVM: Allow ULRI to restrict UserLocal register · cef061d0
      James Hogan 提交于
      The ULRI bit in Config3 specifies whether the UserLocal register is
      implemented, but it is assumed to always be set. Now that the Config
      registers can be modified by userland, allow Config3.ULRI to be cleared
      and check ULRI before allowing the corresponding bit to be set in
      HWREna.
      
      In fact any HWREna bits corresponding to unimplemented RDHWR registers
      should read as zero and be ignored on write, so we actually prevent
      other unimplemented bits being set too.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      cef061d0
    • J
      MIPS: KVM: Don't hardcode restored HWREna · b937ff62
      James Hogan 提交于
      KVM modifies CP0_HWREna during guest execution so it can trap and
      emulate RDHWR instructions, however it always restores the hardcoded
      value 0x2000000F. This assumes the presence of the UserLocal register,
      and the absence of any implementation dependent or future HW registers.
      
      Fix by exporting the value that traps.c write into CP0_HWREna, and
      loading from there instead of hard coding.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Acked-by: NRalf Baechle <ralf@linux-mips.org>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      b937ff62
    • J
      MIPS: Clean up RDHWR handling · aff565aa
      James Hogan 提交于
      No preprocessor definitions are used in the handling of the registers
      accessible with the RDHWR instruction, nor the corresponding bits in the
      CP0 HWREna register.
      
      Add definitions for both the register numbers (MIPS_HWR_*) and HWREna
      bits (MIPS_HWRENA_*) in asm/mipsregs.h and make use of them in the
      initialisation of HWREna and emulation of the RDHWR instruction.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Acked-by: NRalf Baechle <ralf@linux-mips.org>
      Cc: David Daney <david.daney@cavium.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      aff565aa
    • J
      MIPS: KVM: List FPU/MSA registers · e5775930
      James Hogan 提交于
      Make KVM_GET_REG_LIST list FPU & MSA registers. Specifically we list all
      32 vector registers when MSA can be enabled, 32 single-precision FP
      registers when FPU can be enabled, and either 16 or 32 double-precision
      FP registers when FPU can be enabled depending on whether FR mode is
      supported (which provides 32 doubles instead of 16 even doubles).
      
      Note, these registers may still be inaccessible depending on the current
      FP mode of the guest.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      e5775930
    • J
      MIPS: KVM: Use raw_cpu_has_fpu in kvm_mips_guest_can_have_fpu() · 19451e51
      James Hogan 提交于
      We need to use kvm_mips_guest_can_have_fpu() when deciding which
      registers to list with KVM_GET_REG_LIST, however it causes warnings with
      preemption since it uses cpu_has_fpu. KVM is only really supported on
      CPUs which have symmetric FPUs, so switch to raw_cpu_has_fpu to avoid
      the warning.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      19451e51
    • J
      MIPS: KVM: Make KVM_GET_REG_LIST dynamic · f5c43bd4
      James Hogan 提交于
      Make the implementation of KVM_GET_REG_LIST more dynamic so that only
      the subset of registers actually available can be exposed to user mode.
      This is important for VZ where some of the guest register state may not
      be possible to prevent the guest from accessing, therefore the user
      process may need to be aware of the state even if it doesn't understand
      what the state is for.
      
      This also allows different MIPS KVM implementations to provide different
      registers to one another, by way of new num_regs(vcpu) and
      copy_reg_indices(vcpu, indices) callback functions, currently just
      stubbed for trap & emulate.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      f5c43bd4
    • J
      MIPS: KVM: Pass all unknown registers to callbacks · cc68d22f
      James Hogan 提交于
      Pass all unrecognised register IDs through to the set_one_reg() and
      get_one_reg() callbacks, not just select ones. This allows
      implementation specific registers to be more easily added without having
      to modify arch/mips/kvm/mips.c.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      cc68d22f
    • J
      MIPS: KVM: Convert emulation to use asm/inst.h · 258f3a2e
      James Hogan 提交于
      Convert various MIPS KVM guest instruction emulation functions to decode
      instructions (and encode translations) using the union mips_instruction
      and related enumerations in asm/inst.h rather than #defines and
      hardcoded values.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Acked-by: NRalf Baechle <ralf@linux-mips.org>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      258f3a2e
    • J
      MIPS: KVM: Factor writing of translated guest instructions · d5cd26bc
      James Hogan 提交于
      The code in kvm_mips_dyntrans.c to write a translated guest instruction
      to guest memory depending on the segment is duplicated between each of
      the functions. Additionally the cache op translation functions assume
      the instruction is in the KSEG0/1 segment rather than KSEG2/3, which is
      generally true but isn't guaranteed.
      
      Factor that code into a new kvm_mips_trans_replace() which handles both
      KSEG0/1 and KSEG2/3.
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      d5cd26bc
    • J
      MIPS: KVM: Fix translation of MFC0 ErrCtl · 66ffc50c
      James Hogan 提交于
      The MIPS KVM dynamic translation is meant to translate "MFC0 rt, ErrCtl"
      instructions into "ADD rt, zero, zero" to zero the destination register,
      however the rt register number was copied into rt of the ADD instruction
      encoding, which is the 2nd source operand. This results in "ADD zero,
      zero, rt" which is a no-op, so only the first execution of each such
      MFC0 from ErrCtl will actually read 0.
      
      Fix the shift to put the rt from the MFC0 encoding into the rd field of
      the ADD.
      
      Fixes: 50c83085 ("KVM/MIPS32: Binary patching of select privileged instructions.")
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      66ffc50c
  2. 15 6月, 2016 1 次提交
    • P
      Merge tag 'kvm-s390-next-4.8-1' of... · f26ed983
      Paolo Bonzini 提交于
      Merge tag 'kvm-s390-next-4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux into HEAD
      
      KVM: s390: Features and fixes for 4.8 part1
      
      Four bigger things:
      1. The implementation of the STHYI opcode in the kernel. This is used
         in libraries like qclib [1] to provide enough information for a
         capacity and usage based software licence pricing. The STHYI content
         is defined by the related z/VM documentation [2]. Its data can be
         composed by accessing several other interfaces provided by LPAR or
         the machine. This information is partially sensitive or root-only
         so the kernel does the necessary filtering.
      2. Preparation for nested virtualization (VSIE). KVM should query the
         proper sclp interfaces for the availability of some features before
         using it. In the past we have been sloppy and simply assumed that
         several features are available. With this we should be able to handle
         most cases of a missing feature.
      3. CPU model interfaces extended by some additional features that are
         not covered by a facility bit in STFLE. For example all the crypto
         instructions of the coprocessor provide a query function. As reality
         tends to be more complex (e.g. export regulations might block some
         algorithms) we have to provide additional interfaces to query or
         set these non-stfle features.
      4. Several fixes and changes detected and fixed when doing 1-3.
      
      All features change base s390 code. All relevant patches have an ACK
      from the s390 or component maintainers.
      
      The next pull request for 4.8 (part2) will contain the implementation
      of VSIE.
      
      [1] http://www.ibm.com/developerworks/linux/linux390/qclib.html
      [2] https://www.ibm.com/support/knowledgecenter/SSB27U_6.3.0/com.ibm.zvm.v630.hcpb4/hcpb4sth.htm
      f26ed983
  3. 14 6月, 2016 14 次提交