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  1. 18 7月, 2013 1 次提交
  3. 10 7月, 2013 1 次提交
    • D
      drm/i915: don't frob mm.suspended when not using ums · db1b76ca
      由 Daniel Vetter 提交于 
      In kernel modeset driver mode we're in full control of the chip,
always. So there's no need at all to set mm.suspended in
i915_gem_idle. Hence move that out into the leavevt ioctl. Since
i915_gem_idle doesn't suspend gem any more we can also drop the
re-enabling for KMS in the thaw function.

Also clean up the handling of mm.suspend at driver load by coalescing
all the assignments.

Stumbled over while reading through our resume code for unrelated
reasons.

v2: Shovel mm.suspended into the (newly created) ums dungeon as
suggested by Chris Wilson. The plan is that once we've completely
stopped relying on the register save/restore code we could shovel even
that in there.

v3: Improve the locking for the entervt/leavevt ioctls a bit by moving
the dev->struct_mutex locking outside of i915_gem_idle. Also don't
clear dev_priv->ums.mm_suspended for the kms case, we allocate it with
kzalloc. Both suggested by Chris Wilson.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v2)
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      db1b76ca
  5. 09 7月, 2013 1 次提交
    • D
      drm/i915: clean up media reset on gm45 · 36c0cc61
      由 Daniel Vetter 提交于 
      Originally I've thought that this fixes up the reset issues on my
gm45, but that was just a red herring due to b0rked testing.

Still I much prefer writing the right values (all other fields are
reserved) instead of potentially dragging gunk around. Hence also
clear the register to 0 after a reset.

Note that Cspec is a bit confused and doesn't explicitly say that all
the other bits in this register are "reserved, mbz" like usually.
Instead they're marked as "r/o, default value = 0" which semantically
amounts to the same thing.

v2: Stop claiming this fixes anything and return 0 if successful
instead of stack garbage.

v3: Pimp the commit message to explain exactly why I think the docs
allow us to ditch the rmw cycle, spurred by a discussion with Chris.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      36c0cc61
  7. 01 7月, 2013 2 次提交
  9. 11 6月, 2013 2 次提交
    • D
      drm/i915: consolidate ->num_shared_dplls assignement · 7c74ade1
      由 Daniel Vetter 提交于 
      In the future this won't be just for pch plls, so move it into the
shared dpll init code.

v2: Bikeshed the uncessary {} away while applying to appease
checkpatch.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1)
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      7c74ade1
    • D
      drm/i915: s/pch_pll/shared_dpll/ · e72f9fbf
      由 Daniel Vetter 提交于 
      For fastboot we need some support to read out the sharing state of
plls, at least for platforms where they can be shared (or freely
assigned at least). Now for ivb we already have pretty extensive
infrastructure for tracking pch plls, and it took us an aweful lot of
tries to get that remotely right. Note that hsw could also share plls,
but even now they're already freely assignable. So we need this on
more than just ivb.

So on top of the usual fastboot fun pll sharing seems to be an
additional step up in fragility. Hence a common infrastructure for all
shared/freely assignable display plls seems to be in order.

The plan is to have a bit of dpll hw state readout code, which can be
used individually, but also to fill in the pipe config. The hw state
cross check code will then use that information to make sure that
after every modeset every pipe still is connected to a pll which still
has the correct configuration - a lot of the pch pll sharing bugs
where due to incorrect sharing.

We start this endeavour with a simple s/pch_pll/shared_dpll/ rename
job.
Reviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      e72f9fbf
  11. 10 6月, 2013 1 次提交
  13. 01 6月, 2013 3 次提交
  15. 21 5月, 2013 1 次提交
  17. 11 5月, 2013 5 次提交
  19. 23 4月, 2013 3 次提交
  21. 18 4月, 2013 4 次提交
  23. 09 4月, 2013 2 次提交
  25. 06 4月, 2013 1 次提交
  27. 02 4月, 2013 1 次提交
  29. 27 3月, 2013 2 次提交
  31. 24 3月, 2013 1 次提交
  33. 23 3月, 2013 3 次提交
  35. 07 3月, 2013 1 次提交
  37. 05 3月, 2013 1 次提交
    • D
      drm/i915: enable irqs earlier when resuming · 15239099
      由 Daniel Vetter 提交于 
      We need it to restore the ilk rc6 context, since the gpu wait no
requires interrupts. But in general having interrupts around should
help in code sanity, since more and more stuff is interrupt driven.

This regression has been introduced in

commit 3e960501
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Tue Nov 27 16:22:54 2012 +0000

    drm/i915: Rearrange code to only have a single method for waiting upon the ring

Like in the driver load code we need to make sure that hotplug
interrupts don't cause havoc with our modeset state, hence block them
with the existing infrastructure. Again we ignore races where we might
loose hotplug interrupts ...

Note that the driver load part of the regression has already been
fixed in

commit 52d7eced
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Sat Dec 1 21:03:22 2012 +0100

    drm/i915: reorder setup sequence to have irqs for output setup

v2: Add a note to the commit message about which patch fixed the
driver load part of the regression. Stable kernels need to backport
both patches.

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=54691
Cc: stable@vger.kernel.org (for 3.8 only, plese backport
			    52d7eced first)
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Reported-and-Tested-by: NIlya Tumaykin <itumaykin@gmail.com>
Reviewed-by: Chris wilson <chris@chris-wilson.co.uk> (v1)
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      15239099
  39. 04 3月, 2013 1 次提交
  41. 20 2月, 2013 3 次提交