- 08 10月, 2018 4 次提交
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由 Chunyan Zhang 提交于
This patch adds the initial support of Secure Digital Host Controller Interface compliant controller found in some latest Spreadtrum chipsets. This patch has been tested on the version of SPRD-R11 controller. R11 is a variant based on SD v4.0 specification. With this driver, R11 mmc can be initialized, can be mounted, read and written. Original-by: NBillows Wu <billows.wu@unisoc.com> Signed-off-by: NChunyan Zhang <chunyan.zhang@unisoc.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Masahiro Yamada 提交于
Here is another TMIO MMC variant found in Socionext UniPhier SoCs. As commit b6147490 ("mmc: tmio: split core functionality, DMA and MFD glue") said, these MMC controllers use the IP from Panasonic. However, the MMC controller in the TMIO (Toshiba Mobile IO) MFD chip was the first upstreamed user of this IP. The common driver code for this IP is now called 'tmio-mmc-core' in Linux although it is a historical misnomer. Anyway, this driver select's MMC_TMIO_CORE to borrow the common code from tmio-mmc-core.c Older UniPhier SoCs (LD4, Pro4, sLD8) support the external DMA engine like renesas_sdhi_sys_dmac.c. The difference is UniPhier SoCs use a single DMA channel whereas Renesas chips request separate channels for RX and TX. Newer UniPhier SoCs (Pro5 and later) support the internal DMA engine like renesas_sdhi_internal_dmac.c The register map is almost the same, so I guess Renesas and Socionext use the same internal DMA hardware. The main difference is, the register offsets are doubled for Renesas. Renesas Socionext SDHI UniPhier DM_CM_DTRAN_MODE 0x820 0x410 DM_CM_DTRAN_CTRL 0x828 0x414 DM_CM_RST 0x830 0x418 DM_CM_INFO1 0x840 0x420 DM_CM_INFO1_MASK 0x848 0x424 DM_CM_INFO2 0x850 0x428 DM_CM_INFO2_MASK 0x858 0x42c DM_DTRAN_ADDR 0x880 0x440 DM_DTRAN_ADDREX --- 0x444 This comes from the difference of host->bus_shift; 2 for Renesas SoCs, and 1 for UniPhier SoCs. Also, the datasheet for UniPhier SoCs defines DM_DTRAN_ADDR and DM_DTRAN_ADDREX as two separate registers. It could be possible to factor out the DMA common code by introducing some hooks to cope with platform quirks, but this patch does not touch that for now. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Acked-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Paul Cercueil 提交于
Depending on MACH_JZ4740 | MACH_JZ4780 prevent us from creating a generic kernel that works on more than one MIPS board. Instead, we just depend on MIPS being set. Signed-off-by: NPaul Cercueil <paul@crapouillou.net> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Srinath Mannam 提交于
Add ACPI support to all IPROC SDHCI variants. Signed-off-by: NSrinath Mannam <srinath.mannam@broadcom.com> Reviewed-by: NRay Jui <ray.jui@broadcom.com> Reviewed-by: NScott Branden <scott.branden@broadcom.com> Reviewed-by: NVladimir Olovyannikov <vladimir.olovyannikov@broadcom.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 16 7月, 2018 1 次提交
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由 Jisheng Zhang 提交于
Add a driver for SDHCI OF Synopsys DesignWare Cores Mobile Storage Signed-off-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org> Acked-by: NAdrian Hunter <adrian.hunter@intel.com>
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- 21 5月, 2018 1 次提交
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由 Liming Sun 提交于
This commit adds extension to the dw_mmc driver for Mellanox BlueField SoC. It updates the UHS_REG_EXT register to bring up the eMMC card on this SoC. Signed-off-by: NLiming Sun <lsun@mellanox.com> Reviewed-by: NDavid Woods <dwoods@mellanox.com> Reviewed-by: NShawn Lin <shawn.lin@rock-chips.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 02 5月, 2018 3 次提交
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由 Geert Uytterhoeven 提交于
Remove dependencies on HAS_DMA where a Kconfig symbol depends on another symbol that implies HAS_DMA, and, optionally, on "|| COMPILE_TEST". In most cases this other symbol is an architecture or platform specific symbol, or PCI. Generic symbols and drivers without platform dependencies keep their dependencies on HAS_DMA, to prevent compiling subsystems or drivers that cannot work anyway. This simplifies the dependencies, and allows to improve compile-testing. Signed-off-by: NGeert Uytterhoeven <geert@linux-m68k.org> Reviewed-by: NMark Brown <broonie@kernel.org> Acked-by: NRobin Murphy <robin.murphy@arm.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Nan Li 提交于
Explicitly update the docomentation to support the Meson-AXG platform. Signed-off-by: NNan Li <nan.li@amlogic.com> Signed-off-by: NYixun Lan <yixun.lan@amlogic.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org> Acked-by: NKevin Hilman <khilman@baylibre.com>
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由 Alex Smith 提交于
Add support for the JZ4780 MMC controller to the jz47xx_mmc driver. There are a few minor differences from the 4740 to the 4780 that need to be handled, but otherwise the controllers behave the same. The IREG and IMASK registers are expanded to 32 bits. Additionally, some error conditions are now reported in both STATUS and IREG. Writing IREG before reading STATUS causes the bits in STATUS to be cleared, so STATUS must be read first to ensure we see and report error conditions correctly. Signed-off-by: NAlex Smith <alex.smith@imgtec.com> Signed-off-by: NPaul Cercueil <paul@crapouillou.net> Tested-by: NMathieu Malaterre <malat@debian.org> Signed-off-by: NEzequiel Garcia <ezequiel@collabora.co.uk> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 26 3月, 2018 1 次提交
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由 Arnd Bergmann 提交于
The blackfin architecture is getting removed, so this one is obsolete now as well. Acked-by: NUlf Hansson <ulf.hansson@linaro.org> Acked-by: NAaron Wu <aaron.wu@analog.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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- 15 3月, 2018 1 次提交
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由 tianshuliang 提交于
Hi3798CV200 SoC extends the dw-mshc controller for additional clock and bus control. Add support for these extensions. Signed-off-by: Ntianshuliang <tianshuliang@hisilicon.com> Signed-off-by: NJiancheng Xue <xuejiancheng@hisilicon.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org> Reviewed-by: NShawn Lin <shawn.lin@rock-chips.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 02 2月, 2018 1 次提交
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由 Ulf Magnusson 提交于
Blank help texts are probably either a typo, a Kconfig misunderstanding, or some kind of half-committing to adding a help text (in which case a TODO comment would be clearer, if the help text really can't be added right away). Best to remove them, IMO. Signed-off-by: NUlf Magnusson <ulfalizer@gmail.com> Acked-by: NRandy Dunlap <rdunlap@infradead.org> Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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- 31 1月, 2018 1 次提交
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由 Geert Uytterhoeven 提交于
If NO_DMA=y: ERROR: "bad_dma_ops" [drivers/mmc/host/renesas_sdhi_sys_dmac.ko] undefined! ERROR: "bad_dma_ops" [drivers/mmc/host/renesas_sdhi_internal_dmac.ko] undefined! Add dependencies on HAS_DMA to fix this. Fixes: e578afab ("mmc: renesas_sdhi: remove wrong depends on to enable compile test") Signed-off-by: NGeert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 16 1月, 2018 1 次提交
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由 Shawn Lin 提交于
Add CQHCI initialization and implement CQHCI operations for Arasan SDHCI variant host, namely arasan,sdhci-5.1, which is used by Rockchip RK3399 platform. Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 11 1月, 2018 1 次提交
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由 Ard Biesheuvel 提交于
The Fujitsu SDH30 SDHCI controller may be described as a SCX0002 ACPI device on ACPI platforms incorporating the Socionext SynQuacer SoC. Given that mmc_of_parse() has already been made ACPI/DT agnostic, making the SDH30 driver ACPI capable is actually rather simple: all we need to do is make the call to sdhci_get_of_property() [which does not set any properties we care about] and the clock handling dependent on whether we are dealing with a DT device, and exposing the ACPI id via the platform_driver struct and the module metadata. Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 18 12月, 2017 1 次提交
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由 Masahiro Yamada 提交于
ARCH_RENESAS is a stronger condition than (ARM || ARM64). If ARCH_RENESAS is enabled, (ARM || ARM64) is met as well. What is worse, the first depends on line prevents COMPILE_TEST from enabling this driver. It should be removed. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Acked-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 15 12月, 2017 1 次提交
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由 Masahiro Yamada 提交于
The description in the Makefile is odd. Fix the CONFIG selection in a cleaner way. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Acked-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 11 12月, 2017 2 次提交
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由 Adrian Hunter 提交于
Add CQHCI initialization and implement CQHCI operations for Intel GLK. Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org> Tested-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Venkat Gopalakrishnan 提交于
This patch adds CMDQ support for command-queue compatible hosts. Command queue is added in eMMC-5.1 specification. This enables the controller to process upto 32 requests at a time. Adrian Hunter contributed renaming to cqhci, recovery, suspend and resume, cqhci_off, cqhci_wait_for_idle, and external timeout handling. Signed-off-by: NAsutosh Das <asutoshd@codeaurora.org> Signed-off-by: NSujit Reddy Thumma <sthumma@codeaurora.org> Signed-off-by: NKonstantin Dorfman <kdorfman@codeaurora.org> Signed-off-by: NVenkat Gopalakrishnan <venkatg@codeaurora.org> Signed-off-by: NSubhash Jadavani <subhashj@codeaurora.org> Signed-off-by: NRitesh Harjani <riteshh@codeaurora.org> Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org> Tested-by: NLinus Walleij <linus.walleij@linaro.org>
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- 29 11月, 2017 1 次提交
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由 Rui Feng 提交于
Because Realtek card reader drivers are pcie and usb drivers, and they bridge mmc subsystem and memstick subsystem, they are not mfd drivers. Greg and Lee Jones had a discussion about where to put the drivers, the result is that misc is a good place for them, so I move all files to misc. If I don't move them to a right place, I can't add any patch for this driver. Signed-off-by: NRui Feng <rui_feng@realsil.com.cn> Reviewed-by: NDaniel Bristot de Oliveira <bristot@redhat.com> Acked-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NUlf Hansson <ulf.hansson@linaro.org> Acked-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org> Tested-by: NPerry Yuan <perry_yuan@dell.com> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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- 30 10月, 2017 3 次提交
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由 Carlo Caione 提交于
Add a driver for the SDIO/MMC host found on the Amlogic Meson SoCs. This is an MMC controller which provides an interface between the application processor and various memory cards. It supports the SD specification v2.0 and the eMMC specification v4.41. The controller provides an internal "mux" which allows connecting up to three MMC devices to it. Only one device can be used at a time though since the registers are shared across all devices. The driver takes care of synchronizing access (similar to the dw_mmc driver). The maximum supported bus-width is 4-bits. Amlogic's GPL kernel sources call the corresponding driver "aml_sdio" to differentiate it from the other MMC controller in (at least the Meson8 and Meson8b) the SoCs (they call the other drivers aml_sdhc and aml_sdhc_m8, which seem to support a bus-width of up to 8-bits). This means that there are three different MMC host controller IP blocks from Amlogic (each of them with completely own register layout and features): - "SDIO": 1 and 4 bit bus width, support for high-speed modes up to UHS-I SDR50, part of Meson6, Meson8 and Meson8b (the driver from this patch targets this controller) - "SDHC": 1, 4 and 8 bit bus width, compatible with standard iNAND interface, support for speeds up to HS200 and MMC spec up to version 4.5x, part of Meson8 and Meson8b SoCs (there is no mainline driver for this controller yet) - "SDEMMC": 1, 4 and 8 bit bus width, support for speeds up to HS400 and MMC spec up to version 5.0, part of the Meson GX (64-bit) SoCs (supported by the meson-gx MMC host driver) Signed-off-by: NCarlo Caione <carlo@endlessm.com> Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Jan Glauber 提交于
Without the ThunderX/OcteonTx GPIO driver the MMC driver would not power up any MMC devices. Therefore add a dependency to the GPIO driver and remove the unneeded GPIOLIB dependency. Signed-off-by: NJan Glauber <jglauber@cavium.com> Acked-by: NDavid Daney <david.daney@cavium.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Vijay Viswanath 提交于
Enable CONFIG_MMC_SDHCI_IO_ACCESSORS so that SDHC controller specific register read and write APIs, if registered, can be used. Signed-off-by: NVijay Viswanath <vviswana@codeaurora.org> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 22 9月, 2017 1 次提交
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由 Kishon Vijay Abraham I 提交于
Create a new sdhci-omap driver to configure the eMMC/SD/SDIO controller in TI's OMAP SoCs making use of the SDHCI core library. For OMAP specific configurations, populate sdhci_ops with OMAP specific callbacks and use SDHCI quirks. Enable only high speed mode for both SD and eMMC here and add other UHS mode support later. Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 08 9月, 2017 1 次提交
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由 Wolfram Sang 提交于
MMC_DEBUG was moved and one letter got strangely capitalized. Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 30 8月, 2017 5 次提交
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由 Srinivas Kandagatla 提交于
It does not make sense for qcom dml code to be a seperate module, as this has just 2 helper functions specific to qcom, and used directly by mmci driver, so just compile this along with main mmci driver. This would also fix issues arrising due to Kconfig combinations between mmci and qcom dml. Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Ian Molton 提交于
I cannot see why this is needed. kmap() should be safe in this case. Signed-off-by: NIan Molton <ian@mnementh.co.uk> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Shawn Lin 提交于
We have removed all code depending on CONFIG_MMC_DEBUG from mmc core now. So it's safe to make CONFIG_MMC_DEBUG just for host drivers only and we expect to kill this option in the future. Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Ivan Mikhaylov 提交于
shdci-st driver can be used for ppc476 fsp2 soc. Signed-off-by: NIvan Mikhaylov <ivan@de.ibm.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Simon Horman 提交于
Add a new variant of the SDHI driver to support R-Car Gen3 with DMA via on-chip bus mastering. Since the DMAC is in a part of the SDHI module it is not suitable to be used via DMA Engine. Clearing of DM_CM_INFO1 after DMA thanks to Dirk Behme Cc: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: NAi Kyuse <ai.kyuse.uw@renesas.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 20 6月, 2017 2 次提交
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由 Simon Horman 提交于
Rename the source file SDHI. A follow-up patch will make it a library file used by a different top-level module file. The name "renesas" is chosen as the SDHI driver is applicable to a wider range of SoCs than SH-Mobile it seems to be a more appropriate name. However, the SDHI driver source itself, is left as sh_mobile_sdhi to avoid unnecessary churn. the name "core" was chosen to reflect the desired role of this file, to provide core functionality to the sdhi driver. A follow-up patch will move the file into that role. Internal symbols have also been renamed to reflect the filename change. The .name member of struct platform_driver and parameter to MODULE_ALIAS() have not been changed in order to avoid the complication of potentially breaking SH SoCs which still use platform drivers. Signed-off-by: NSimon Horman <horms+renesas@verge.net.au> Acked-by: NArnd Bergmann <arnd@arndb.de> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Andy Shevchenko 提交于
AVR32 is gone. Now it's time to clean up the driver by removing leftovers that was used by AVR32 related code. Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: NLudovic Desroches <ludovic.desroches@microchip.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 25 4月, 2017 4 次提交
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由 Steven J. Hill 提交于
Add platform driver for Octeon SOCs. Signed-off-by: NSteven J. Hill <Steven.Hill@cavium.com> Signed-off-by: NDavid Daney <david.daney@cavium.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Hu Ziji 提交于
Add Xenon eMMC/SD/SDIO host controller core functionality. Add Xenon specific initialization process. Add Xenon specific mmc_host_ops APIs. Add Xenon specific register definitions. Add CONFIG_MMC_SDHCI_XENON support in drivers/mmc/host/Kconfig. Marvell Xenon SDHC conforms to SD Physical Layer Specification Version 3.01 and is designed according to the guidelines provided in the SD Host Controller Standard Specification Version 3.00. Signed-off-by: NHu Ziji <huziji@marvell.com> Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Jan Glauber 提交于
Add a platform driver for ThunderX ARM SOCs. Signed-off-by: NJan Glauber <jglauber@cavium.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Eric Anholt 提交于
The 2835 has two SD controllers: The Arasan sdhci controller (supported by the iproc driver) and a custom sdhost controller. This patch adds a driver for the latter. The sdhci controller supports both sdcard and sdio. The sdhost controller supports the sdcard only, but has better performance. Also note that the rpi3 has sdio wifi, so driving the sdcard with the sdhost controller allows to use the sdhci controller for wifi support. The configuration is done by devicetree via pin muxing. Both SD controller are available on the same pins (2 pin groups = pin 22 to 27 + pin 48 to 53). So it's possible to use both SD controllers at the same time with different pin groups. The code was originally written by Phil Elwell in the downstream Rasbperry Pi tree. In preparation for the upstream merge it was cleaned up and the code base was moderized by Eric Anholt, Stefan Wahren and Gerd Hoffmann. Signed-off-by: NEric Anholt <eric@anholt.net> Signed-off-by: NStefan Wahren <stefan.wahren@i2se.com> Signed-off-by: NGerd Hoffmann <kraxel@redhat.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 13 2月, 2017 1 次提交
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由 Jun Nie 提交于
This platform driver adds initial support for the DW host controller found on ZTE SoCs. It has been tested on ZX296718 EVB board currently. More support on timing tuning will be added when hardware is available. Signed-off-by: NJun Nie <jun.nie@linaro.org> Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 08 12月, 2016 1 次提交
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由 Masahiro Yamada 提交于
Add a driver for the Cadence SD4HC SD/SDIO/eMMC Controller. For SD, it basically relies on the SDHCI standard code. For eMMC, this driver provides some callbacks to support the hardware part that is specific to this IP design. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 05 12月, 2016 1 次提交
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由 Masahiro Yamada 提交于
I see no override of read/write callbacks in sdhci-of-at91.c. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Acked-by: NLudovic Desroches <ludovic.desroches@atmel.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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- 29 11月, 2016 1 次提交
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由 yangbo lu 提交于
The eSDHC of T4240-R1.0-R2.0 has incorrect vender version and spec version. Acturally the right version numbers should be VVN=0x13 and SVN = 0x1. This patch adds the GUTS driver support for eSDHC driver to match SoC. And fix host version to avoid that incorrect version numbers break down the ADMA data transfer. Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com> Acked-by: NUlf Hansson <ulf.hansson@linaro.org> Acked-by: NScott Wood <oss@buserror.net> Acked-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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