- 21 8月, 2021 1 次提交
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由 周琰杰 (Zhou Yanjie) 提交于
1.Add OST_CLK_EVENT_TIMER for new XBurst®1 SoCs. 2.Add OST_CLK_EVENT_TIMER0 to OST_CLK_EVENT_TIMER15 for new XBurst®2 SoCs. Signed-off-by: N周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/1626370605-120775-1-git-send-email-zhouyanjie@wanyeetech.com
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- 16 8月, 2021 1 次提交
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由 Dmitry Osipenko 提交于
SMB347 can supply power to USB VBUS, which is required by OTG-cable devices that want to switch USB port into the host mode. Add USB VBUS regulator properties. Reviewed-by: NRob Herring <robh@kernel.org> Signed-off-by: NDmitry Osipenko <digetx@gmail.com> Signed-off-by: NSebastian Reichel <sebastian.reichel@collabora.com>
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- 09 8月, 2021 1 次提交
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由 Georgi Djakov 提交于
Add compatibles and port definitions for the SC8180x RPMH interconnect providers. Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org> [bjorn: Split defines from driver patch and added binding update] Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: NRob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210723194243.3675795-1-bjorn.andersson@linaro.orgSigned-off-by: NGeorgi Djakov <djakov@kernel.org>
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- 08 8月, 2021 1 次提交
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由 Jonathan Marek 提交于
Document a new phy-type property which will be used to determine whether the phy should operate in D-PHY or C-PHY mode. Signed-off-by: NJonathan Marek <jonathan@marek.ca> Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20210617144349.28448-3-jonathan@marek.caAcked-by: NRob Herring <robh@kernel.org> Signed-off-by: NDmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: NRob Clark <robdclark@chromium.org>
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- 01 8月, 2021 1 次提交
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由 Christophe Branchereau 提交于
The JZ4760(B) socs have 3 AUX inputs, add an entry to prepare including the one named AUX in the sadc driver. Leaving the rest untouched as it's ABI. Signed-off-by: NChristophe Branchereau <cbranchereau@gmail.com> Reviewed-by: NPaul Cercueil <paul@crapouillou.net> Acked-by: NRob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210726082033.351533-3-cbranchereau@gmail.comSigned-off-by: NJonathan Cameron <Jonathan.Cameron@huawei.com>
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- 26 7月, 2021 1 次提交
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由 Lad Prabhakar 提交于
Add P0_DIV2 core clock required for CANFD module. CANFD core clock is sourced from P0_DIV2 referenced from HW manual Rev.0.50. Signed-off-by: NLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: NBiju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210719143811.2135-4-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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- 21 7月, 2021 1 次提交
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由 Sibi Sankar 提交于
Add PDC Global reset controller bindings for SC7280 SoCs. Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NSibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/1619693465-5724-4-git-send-email-sibis@codeaurora.orgSigned-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
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- 20 7月, 2021 1 次提交
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由 Iskren Chernev 提交于
Add compatible and constants for the power domains exposed by the RPM in the Qualcomm SM4250/6115 platforms. Signed-off-by: NIskren Chernev <iskren.chernev@gmail.com> Acked-by: NRob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210627185927.695411-5-iskren.chernev@gmail.comSigned-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
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- 12 7月, 2021 1 次提交
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由 Biju Das 提交于
Update clock and reset definitions as per RZ/G2L_clock_list_r02_02.xlsx and RZ/G2L HW(Rev.0.50) manual. Update {GIC,IA55,SCIF} clock and reset entries in the CPG driver, and separate reset from module clocks in order to handle them efficiently. Update the SCIF0 clock and reset index in the SoC DTSI. Signed-off-by: NBiju Das <biju.das.jz@bp.renesas.com> Reviewed-by: NLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210626081344.5783-6-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20210626081344.5783-7-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20210626081344.5783-8-biju.das.jz@bp.renesas.com [geert: Squashed 3 commits] Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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- 29 6月, 2021 3 次提交
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由 Gabriel Fernandez 提交于
Add ID to SCMI0 to exposes reset controller for the MCU HOLD BOOT resource. Signed-off-by: NArnaud Pouliquen <arnaud.pouliquen@foss.st.com> Signed-off-by: NGabriel Fernandez <gabriel.fernandez@foss.st.com> Acked-by: NRob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210617051814.12018-10-gabriel.fernandez@foss.st.comSigned-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Gabriel Fernandez 提交于
stm32mp15 TZ secure firmware provides SCMI reset domains for secure resources. This change defines the SCMI reset domain identifiers used by SCMI agents and servers. Stm32mp15 TZ secure firmware provides SCMI clocks for oscillators, some PLL output and few secure aware interfaces. This change defines the SCMI clock identifiers used by SCMI agents and servers. Server SCMI0 exposes reset controllers for resources under RCC[TZEN] configuration control. Signed-off-by: NEtienne Carriere <etienne.carriere@foss.st.com> Signed-off-by: NGabriel Fernandez <gabriel.fernandez@foss.st.com> Acked-by: NRob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210617051814.12018-9-gabriel.fernandez@foss.st.comSigned-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Gabriel Fernandez 提交于
stm32mp15 TZ secure firmware provides SCMI clocks for oscillators, some PLL output and few secure aware interfaces. This change defines the SCMI clock identifiers used by SCMI agents and servers. Server SCMI0 exposes clocks and reset controllers for resources under RCC[TZEN] configuration control. Server SCMI1 exposes clocks for resources under RCC[MCKPROT] control. Signed-off-by: NEtienne Carriere <etienne.carriere@foss.st.com> Signed-off-by: NGabriel Fernandez <gabriel.fernandez@foss.st.com> Acked-by: NRob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210617051814.12018-8-gabriel.fernandez@foss.st.comSigned-off-by: NStephen Boyd <sboyd@kernel.org>
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- 28 6月, 2021 5 次提交
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由 Dongjiu Geng 提交于
Add DT bindings documentation for hi3559a SoC clock. Signed-off-by: NDongjiu Geng <gengdongjiu@huawei.com> Reviewed-by: NRob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1616498973-47067-2-git-send-email-gengdongjiu1@gmail.comSigned-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Paul Cercueil 提交于
Add the CGU code and the compatible string to the TCU driver to support the JZ4760 SoC. Signed-off-by: NPaul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-7-paul@crapouillou.netSigned-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Cristian Ciocaltea 提交于
Add the missing NIC and ETHERNET clock bindings constants for Actions Semi Owl S500 SoC. Signed-off-by: NCristian Ciocaltea <cristian.ciocaltea@gmail.com> Acked-by: NRob Herring <robh@kernel.org> Reviewed-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/1d0902cf073f76a1a602410061481ccb3fc36a72.1623354574.git.cristian.ciocaltea@gmail.comSigned-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Jonathan Marek 提交于
Add device tree bindings for camera clock controller for Qualcomm Technology Inc's SM8250 SoC. Signed-off-by: NJonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20210609022051.2171-3-jonathan@marek.caReviewed-by: NRob Herring <robh@kernel.org> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Martin Botka 提交于
Document the newly added SM6125 GCC driver. Signed-off-by: NMartin Botka <martin.botka@somainline.org> Link: https://lore.kernel.org/r/20210605121040.282053-1-martin.botka@somainline.orgReviewed-by: NRob Herring <robh@kernel.org> Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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- 17 6月, 2021 1 次提交
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由 Hao Fang 提交于
s/Hisilicon/HiSilicon/. It should use capital S, according to the official website https://www.hisilicon.com/en. Signed-off-by: NHao Fang <fanghao11@huawei.com> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NWei Xu <xuwei5@hisilicon.com>
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- 15 6月, 2021 1 次提交
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由 Gabriel David 提交于
This patch adds bindings required for Quinary MI2S ports on AFE. Signed-off-by: NGabriel David <ultracoolguy@disroot.org> Reviewed-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20210605022206.13226-2-ultracoolguy@disroot.orgSigned-off-by: NMark Brown <broonie@kernel.org>
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- 14 6月, 2021 2 次提交
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由 Lucas Stach 提交于
Remove the PLL clock gates as the allowing to gate the sys1_pll_266m breaks the uSDHC module which is sporadically unable to enumerate devices after this change. Also it makes AMP clock management harder with no obvious benefit to Linux, so just revert the change. Link: https://lore.kernel.org/r/20210528180135.1640876-1-l.stach@pengutronix.de Fixes: b04383b6 ("clk: imx8mq: Define gates for pll1/2 fixed dividers") Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Reviewed-by: NAbel Vesa <abel.vesa@nxp.com> Signed-off-by: NAbel Vesa <abel.vesa@nxp.com>
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由 Dong Aisheng 提交于
Legacy scu clock binding are not maintained anymore, it has a very limited clocks supported during initial upstreaming and obviously unusable by products. So it's meaningless to keep it in kernel which worse the code readability. Remove it to keep code much cleaner. Signed-off-by: NDong Aisheng <aisheng.dong@nxp.com> Reviewed-by: NAbel Vesa <abel.vesa@nxp.com> Signed-off-by: NAbel Vesa <abel.vesa@nxp.com>
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- 12 6月, 2021 1 次提交
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由 Adam Ford 提交于
The i.MX8M Nano has a similar power domain controller to that of the mini, but it isn't fully compatible, so it needs a separate binding and power domain tables. Add the bindings and tables. Signed-off-by: NAdam Ford <aford173@gmail.com> Reviewed-by: NKrzysztof Kozlowski <krzk@kernel.org> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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- 11 6月, 2021 1 次提交
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由 Konrad Dybcio 提交于
This SoC while being from 8916 era, makes use of the newer-style, floor-level management, instead of the older floor-corner. Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NKonrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210131013233.54666-1-konrad.dybcio@somainline.orgSigned-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
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- 10 6月, 2021 1 次提交
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由 Lad Prabhakar 提交于
Define RZ/G2L (R9A07G044) Clock Pulse Generator Core Clock and module clock outputs, as listed in Table 8.3 ("Clock List") of the RZ/G2L Hardware User's Manual (Rev.0.42, Feb.2021). Signed-off-by: NLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: NBiju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-7-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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- 04 6月, 2021 3 次提交
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由 Kyle Tso 提交于
Add the VDO definition for USB PD rev 2.0 in the bindings and define a new property snk-vdos-v1 containing legacy VDOs as the responses to the port partner which only supports PD rev 2.0. Reviewed-by: NRob Herring <robh@kernel.org> Signed-off-by: NKyle Tso <kyletso@google.com> Link: https://lore.kernel.org/r/20210601123151.3441914-3-kyletso@google.comSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Kyle Tso 提交于
BIT macro is not defined. Replace it with generic bit operations. Fixes: 630dce28 ("dt-bindings: connector: Add SVDM VDO properties") Reviewed-by: NRob Herring <robh@kernel.org> Signed-off-by: NKyle Tso <kyletso@google.com> Link: https://lore.kernel.org/r/20210527121029.583611-1-kyletso@google.comSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
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由 Seiya Wang 提交于
Remove CLK_INFRA_CA57SEL for MT8173 since it's no longer used. Acked-by: NRob Herring <robh@kernel.org> Reviewed-by: NMatthias Brugger <matthias.bgg@gmail.com> Signed-off-by: NSeiya Wang <seiya.wang@mediatek.com> Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>
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- 02 6月, 2021 4 次提交
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由 Guru Das Srinagesh 提交于
Add a header file listing all of the IRQs that Qualcomm Technologies, Inc. PM8008 supports. The constants defined in this file may be used in the client device tree node to specify interrupts. Signed-off-by: NGuru Das Srinagesh <gurus@codeaurora.org> Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 ChiYuan Huang 提交于
Adds DT binding document for Richtek RT4831 backlight. Signed-off-by: NChiYuan Huang <cy_huang@richtek.com> Reviewed-by: NDaniel Thompson <daniel.thompson@linaro.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Bjorn Andersson 提交于
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210511041719.591969-2-bjorn.andersson@linaro.orgAcked-by: NRob Herring <robh@kernel.org> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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由 Konrad Dybcio 提交于
Add device tree bindings for global clock controller on MDM9607 SoC. Signed-off-by: NKonrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210313020310.386152-1-konrad.dybcio@somainline.orgAcked-by: NRob Herring <robh@kernel.org> Signed-off-by: NStephen Boyd <sboyd@kernel.org>
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- 01 6月, 2021 1 次提交
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由 Sibi Sankar 提交于
Add WPSS remote processor client index to Inter-Processor Communication Controller (IPCC) block. Acked-by: NRob Herring <robh@kernel.org> Reviewed-by: NStephen Boyd <swboyd@chromium.org> Signed-off-by: NSibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/1619508824-14413-2-git-send-email-sibis@codeaurora.orgSigned-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
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- 27 5月, 2021 2 次提交
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由 Fabien Parent 提交于
Add binding documentation for MT8365 Pin controller. Signed-off-by: NFabien Parent <fparent@baylibre.com> Acked-by: NRob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210519162409.3755679-1-fparent@baylibre.comSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Lucas Stach 提交于
Adding defines for i.MX8MM GPC power domains. Tested-by: NFrieder Schrempf <frieder.schrempf@kontron.de> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NPeng Fan <peng.fan@nxp.com> Signed-off-by: NShawn Guo <shawnguo@kernel.org>
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- 26 5月, 2021 1 次提交
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由 Bjorn Andersson 提交于
Add compatible and constants for the power domains exposed by the RPMH in the Qualcomm SC8180X platform. Reviewed-by: NShawn Guo <shawn.guo@linaro.org> Reviewed-by: NVinod Koul <vkoul@kernel.org> Acked-by: NRob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210120225037.1611353-1-bjorn.andersson@linaro.orgSigned-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
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- 25 5月, 2021 1 次提交
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由 Mark Kettenis 提交于
The Apple GPIO controller is a simple combined pin and GPIO conroller present on Apple ARM SoC platforms, including various iPhone and iPad devices and the "Apple Silicon" Macs. Signed-off-by: NMark Kettenis <kettenis@openbsd.org> Link: https://lore.kernel.org/r/20210520171310.772-2-mark.kettenis@xs4all.nlSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 19 5月, 2021 1 次提交
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由 ChiYuan Huang 提交于
Adds DT binding document for Richtek RT4831 backlight. Signed-off-by: NChiYuan Huang <cy_huang@richtek.com> Reviewed-by: NDaniel Thompson <daniel.thompson@linaro.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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- 11 5月, 2021 1 次提交
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由 Odelu Kukatla 提交于
The Qualcomm SC7280 platform has several bus fabrics that could be controlled and tuned dynamically according to the bandwidth demand. Signed-off-by: NOdelu Kukatla <okukatla@codeaurora.org> Reviewed-by: NRob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1619517059-12109-2-git-send-email-okukatla@codeaurora.orgSigned-off-by: NGeorgi Djakov <djakov@kernel.org>
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- 10 5月, 2021 1 次提交
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由 Elaine Zhang 提交于
According to a description from TRM, add all the power domains Signed-off-by: NElaine Zhang <zhangqing@rock-chips.com> Reviewed-by: NEnric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: NJohan Jonker <jbx6244@gmail.com> Acked-by: NRob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210417112952.8516-11-jbx6244@gmail.comSigned-off-by: NHeiko Stuebner <heiko@sntech.de>
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- 04 5月, 2021 1 次提交
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由 Greentime Hu 提交于
We add pcie_aux clock in this patch so that pcie driver can use clk_prepare_enable() and clk_disable_unprepare() to enable and disable pcie_aux clock. Link: https://lore.kernel.org/r/20210504105940.100004-2-greentime.hu@sifive.comSigned-off-by: NGreentime Hu <greentime.hu@sifive.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: NStephen Boyd <sboyd@kernel.org>
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