- 03 1月, 2017 1 次提交
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由 Simon Horman 提交于
Use the SoC-specific compat string for mmcif in DT for the sh73a0 SoC. This is in keeping with the use of compat strings for mmcif for other Renesas ARM based SoCs. Signed-off-by: NSimon Horman <horms+renesas@verge.net.au> Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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- 04 11月, 2016 1 次提交
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由 Geert Uytterhoeven 提交于
As of commit 9c0da3cc ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"), including skeleton.dtsi is deprecated. This fixes the following warning with W=1: Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Acked-by: NMark Rutland <mark.rutland@arm.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 30 5月, 2016 1 次提交
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由 Geert Uytterhoeven 提交于
Warning (unit_address_vs_reg): Node /cache-controller has a reg or ranges property, but no unit name Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 20 4月, 2016 1 次提交
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由 Geert Uytterhoeven 提交于
The ARM TWD interrupt is a private peripheral interrupt (PPI), and per the ARM GIC documentation, whether the type for PPIs can be set is IMPLEMENTATION DEFINED. For SH-Mobile AG5 devices the PPI type cannot be set, and so when we attempt to set the type for the ARM TWD interrupt it fails. This has gone unnoticed because it fails silently, and because we cannot re-configure the type it has had no impact. Nevertheless fix the type for the TWD interrupt so that it matches the hardware configuration. Based on patches by Jon Hunter for Tegra20/30 and OMAP4. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 28 3月, 2016 1 次提交
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由 Simon Horman 提交于
* Fixed rate and fixed factor clocks do not require an clock-output-names property. * Since 07705583 ("clk: shmobile: div6: Make clock-output-names optional") Renesas div6 clocks do not require a clock-output-names property. In the above cases there is only one clock output and its name is taken from that of the clock node. Accordingly, remove the unnecessary clock-output-names properties and as necessary update the node names. The clock-output-names property is left in place for the zb_clk which is thus treated as a special case as the MSTP clock driver (clk-mstp.c) explicitly looks for a clock with node name zb_clk for the r8a73a4 and sh73a0 SoCs. Signed-off-by: NSimon Horman <horms+renesas@verge.net.au> Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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- 10 2月, 2016 2 次提交
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由 Laurent Pinchart 提交于
The clock is really the device functional clock, not the interface clock. Rename it. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Simon Horman 提交于
Use GIC_* defines for GIC interrupt cells in sh73a0 device tree. Signed-off-by: NSimon Horman <horms+renesas@verge.net.au> Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be>
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- 01 12月, 2015 2 次提交
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由 Geert Uytterhoeven 提交于
The sh73a0 has 4 MSIOF devices, located in the A3SP power area. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Geert Uytterhoeven 提交于
The 4 MSIOF clocks are MSTP clocks, and children of the SUB clock. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 25 11月, 2015 1 次提交
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由 Geert Uytterhoeven 提交于
Add the missing L2 cache-controller node, and link the CPU nodes to it. This will allow migration to the generic l2c OF initialization. The L2 cache is an ARM L2C-310 (r3p1), of size 512 KiB (64 KiB x 8 ways). Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 05 8月, 2015 1 次提交
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由 Geert Uytterhoeven 提交于
If a GPIO driver uses gpiochip_add_pin_range() (which is usually the case for GPIO/PFC combos), the GPIO hogging mechanism configured from DT doesn't work: requesting hog GPIO led1-high (chip sh73a0_pfc, offset 20) failed The actual error code is -517 == -EPROBE_DEFER. The problem is that PFC+GPIO registration is handled in multiple steps: 1. pinctrl_register(), 2. gpiochip_add(), 3. gpiochip_add_pin_range(). Configuration of the hogs is handled in gpiochip_add(): gpiochip_add of_gpiochip_add of_gpiochip_scan_hogs gpiod_hog gpiochip_request_own_desc __gpiod_request chip->request pinctrl_request_gpio pinctrl_get_device_gpio_range However, at this point the GPIO controller hasn't been added to pinctrldev_list yet, so the range can't be found, and the operation fails with -EPROBE_DEFER. To fix this, add a "gpio-ranges" property to the gpio device node, so the ranges are added by of_gpiochip_add_pin_range(), which is called by of_gpiochip_add() before the call to of_gpiochip_scan_hogs(). Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 11 5月, 2015 1 次提交
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由 Geert Uytterhoeven 提交于
irqpin -> interrupt-controller Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 28 4月, 2015 1 次提交
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由 Geert Uytterhoeven 提交于
The single SCIFB on SH-Mobile AG5 is called "scifb", not "scifb8". Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 24 2月, 2015 6 次提交
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由 Geert Uytterhoeven 提交于
Add a device node for the System Controller, with subnodes that represent the hardware power area hierarchy. Hook up all devices to their respective PM domains. Note that unlike on R-Mobile A1 (r8a7740), PM domain D4 can be powered down without ill effects on s2ram behavior, just like on SH-Mobile AP4 (sh7372). Hence we can postpone adding a (minimal) device node for the Coresight-ETM hardware block. The System Controller is also used by the R-Mobile Reset driver, which can now restart the system. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Geert Uytterhoeven 提交于
Add a node for the Private Timer and Watchdog, as found in the Cortex-A9 MPCore. Without this, there's no clocksource available during early kernel initialization, before cmt1 is initialized, leading to a lock-up if CONFIG_CPU_IDLE=y. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Geert Uytterhoeven 提交于
Add a node for the Bus State Controller (BSC) on sh73a0, to which multiple external devices can be connected. The BSC is driven by the ZB clock, and located in PM domain A4S. A reference to the latter will be added later. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Ulrich Hecht 提交于
Specifies clock sources and register bits. Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com> [geert: Drop renesas,src-shift/renesas,src-width, pad to 4 or 8 parents] Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Geert Uytterhoeven 提交于
This clock drives the irqpin controller modules. Before, it was assumed enabled by the bootloader or reset state. By making it available to the driver, we make sure it gets enabled when needed, and allow it to be managed by system or runtime PM. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Laurent Pinchart 提交于
The sh73a0 INTC can't mask interrupts properly most likely due to a hardware bug. Set the control-parent property to delegate masking to the parent interrupt controller. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 15 1月, 2015 1 次提交
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由 Geert Uytterhoeven 提交于
Add device nodes for the two SDRAM Bus State Controllers. The SBSCs are located in the A4BC0 resp. A4BC1 PM domains, which must not be powered down, else the system will crash. References to the A4BC0 and A4BC1 PM domains will be added later. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 08 1月, 2015 1 次提交
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由 Geert Uytterhoeven 提交于
The FSI2 sound node used the generic compatible property only. Add the SoC-specific one, to make it future proof. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Acked-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 21 12月, 2014 2 次提交
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由 Ulrich Hecht 提交于
Assigns clocks to cmt1, i2c*, mmcif, sdhi*, and scif*. Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: NGeert Uytterhoeven <geert+renesas@glider.be> Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Ulrich Hecht 提交于
Declares all sh73a0 clocks supported by the legacy clock framework. Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com> Tested-by: NGeert Uytterhoeven <geert+renesas@glider.be> Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 19 11月, 2014 1 次提交
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由 Geert Uytterhoeven 提交于
The IIC nodes used the generic compatible properties only. This causes the driver to fail when using Standard Speed, as the operational clock is driven by the 104 MHz HP clock: i2c-sh_mobile e6820000.i2c: timing values out of range: L/H=0x208/0x1bf i2c-sh_mobile: probe of e6820000.i2c failed with error -22 Add the SoC-specific compatible property to fix this. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 09 9月, 2014 1 次提交
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由 Ulrich Hecht 提交于
Signed-off-by: NUlrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: NMagnus Damm <damm+renesas@opensource.se> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 22 8月, 2014 2 次提交
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由 Geert Uytterhoeven 提交于
Add an "interrupt-parent = <&gic>;" at the top, which is inherited by all child nodes, so the "interrupt-parent" properties can be removed from the individual child nodes. Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be> Acked-by: NMagnus Damm <damm+renesas@opensource.se> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Magnus Damm 提交于
Add CPU Frequency information to the sh73a0 DTS file. This will allow us to use the shared C code on sh73a0 and KZM9G which reads out the clock frequency from DT and calculates the delay settings from there. Signed-off-by: NMagnus Damm <damm+renesas@opensource.se> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 12 7月, 2014 1 次提交
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由 Simon Horman 提交于
This describes all of the SCIF hardware of the sh73a0. Each node is disabled and may be enabled as necessary by board DTS files. Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 15 4月, 2014 1 次提交
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由 Lucas Stach 提交于
This is likely a copy-and-paste error from the ARM GIC documentation, that has already been fixed. address-cells should have been set to 0, as with the size cells. As having those properties set to 0 is the same thing as not specifying them, drop them completely. Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 19 12月, 2013 1 次提交
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由 Laurent Pinchart 提交于
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 12 12月, 2013 1 次提交
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由 Kuninori Morimoto 提交于
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 10 12月, 2013 4 次提交
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由 Magnus Damm 提交于
Add "renesas,intc-irqpin-sh73a0" to the compatible string for the IRQ pins in case of sh73a0 INTC. This makes the INTC irqpin follow the same style as the other devices and also makes it more future proof. Signed-off-by: NMagnus Damm <damm@opensource.se> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Kuninori Morimoto 提交于
sh73a0 != r8a7740 Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Laurent Pinchart 提交于
Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Kuninori Morimoto 提交于
According to ePAPR spec, this patch tidies up DT node name and related clock. Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 08 10月, 2013 1 次提交
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由 Guennadi Liakhovetski 提交于
Currently all I2C interfaces in all *.dtsi files for various Renesas SoCs are enabled by default. Switch them all off and only enable populated I2C interfaces in board-specific *.dts files. Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Acked-by: NMark Rutland <mark.rutland@arm.com> Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 22 9月, 2013 1 次提交
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由 Guennadi Liakhovetski 提交于
Currently DT compatibility strings of both types can be found in the kernel sources: <unit>-<soc> and <soc>-<unit>, whereas a unique format should be followed and the former one is preferred. This patch converts the SDHI MMC driver and its users to the common standard. This is safe for now, since ATM no real products are using this driver with DT. Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Acked-by: NChris Ball <cjb@laptop.org> [Removed r8a7740.dtsi portion as it is not applicable] Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 31 7月, 2013 1 次提交
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由 Magnus Damm 提交于
Add PMU information to sh73a0.dtsi. With this included KZM9G DT reference may use the PMU. Signed-off-by: NMagnus Damm <damm@opensource.se> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 22 7月, 2013 1 次提交
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由 Laurent Pinchart 提交于
Add a pfc node to the sh73a0 device tree and remove manual pinmux initialization from the corresponding board files. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 18 6月, 2013 1 次提交
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由 Guennadi Liakhovetski 提交于
The convention for Device Tree node names is <device>@<hex-address>, where the part after '@' shouldn't contain the "0x" prefix. Fix the sh73a0.dtsi DT names. Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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