- 20 1月, 2012 1 次提交
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由 Shawn Guo 提交于
With commit 5def51b0 (ARM: 7211/1: smp_twd: get the rate from a clock) hitting mainline, if we do not have a twd_clk for lookup, we will see the following error message in boot log. smp_twd: clock not found: -2 Actually we should add this clock regardless of the error message, so that we can: * Avoid the local timer calibrating at boot time * Make the local timer cpufreq aware on imx6q Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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- 05 1月, 2012 1 次提交
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由 Shawn Guo 提交于
The restart support was missed from the initial imx6q submission. The mxc_restart() does not work for imx6q. Instead, this patch adds the restart for imx6q. Signed-off-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 17 11月, 2011 1 次提交
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由 Richard Zhao 提交于
map_io is the only place to call iotable_init. Signed-off-by: NRichard Zhao <richard.zhao@linaro.org> [shawn.guo: rename imx_clock_map_io() to imx6q_clock_map_io()] Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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- 11 11月, 2011 1 次提交
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由 Shawn Guo 提交于
The following error is seen in some case when mounting rootfs from SD/MMC cards. Waiting for root device /dev/mmcblk0p1... mmc1: host does not support reading read-only switch. assuming write-enable. mmc1: new high speed SDHC card at address b368 mmcblk0: mmc1:b368 SDC 3.74 GiB mmcblk0: p1 mmc1: Timeout waiting for hardware interrupt. mmcblk0: error -110 transferring data, sector 3678224, nr 40, cmd response 0x900, card status 0xc00 end_request: I/O error, dev mmcblk0, sector 3678225 Buffer I/O error on device mmcblk0p1, logical block 458754 lost page write due to I/O error on mmcblk0p1 This patch fixes the problem by lowering the usdhc clock and correcting watermark configuration. Signed-off-by: NShawn Guo <shawn.guo@linaro.org> Cc: Chris Ball <cjb@laptop.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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- 31 10月, 2011 1 次提交
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由 Shawn Guo 提交于
It adds a number of core drivers support for imx6q, including clock, General Power Controller (gpc), Multi Mode DDR Controller(mmdc) and System Reset Controller (src). Signed-off-by: NRanjani Vaidyanathan <ra5478@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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