- 12 4月, 2013 4 次提交
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由 Sascha Hauer 提交于
This adds the clock gates and the binding documentation for PATA and SRTC. Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Martin Fuzzey 提交于
These two clocks connect to external pins and can be muxed to various internal clocks. They are typically used either for debugging or to provide clocks to external chips (eg audio codecs). Currently only the selectable clocks that already exist in the clock tree have been added. Signed-off-by: NMartin Fuzzey <mfuzzey@parkeon.com> Acked-by: NSascha Hauer <s.hauer@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Philipp Zabel 提交于
Query silicon revision to determine clock tree and add post dividers for newer revisions. Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Philipp Zabel 提交于
This patch adds the missing GPU2D and GPU3D mux and gate clocks, and the graphics arbiter gate clock. Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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- 16 2月, 2013 1 次提交
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由 Jason Cooper 提交于
Signed-off-by: NJason Cooper <jason@lakedaemon.net>
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- 10 2月, 2013 2 次提交
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由 Martin Fuzzey 提交于
Signed-off-by: NMartin Fuzzey <mfuzzey@parkeon.com> Acked-by: NSascha Hauer <s.hauer@pengutronix.de> Acked-by: NEvgeniy Polyakov <zbr@ioremap.net> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Peter Chen 提交于
This mxs usbphy is only needs to be on after system boots up, and software never needs to control it anymore. Meanwhile, usbphy's parent needs to be notified if usb is suspend or not. So we design below mxs usbphy usage: - usbphy1_gate and usbphy2_gate: Their parents are dummy clock, we only needs to enable it after system boots up. - usbphy1 and usbphy2 Usage reserved bit for this clock, in that case, the refcount will be updated, but without hardware changing. Signed-off-by: NPeter Chen <peter.chen@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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- 29 1月, 2013 2 次提交
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由 Prashant Gaikwad 提交于
The device tree binding models Tegra30 CAR (Clock And Reset) as a single monolithic clock provider. Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com> [swarren: fixed typo in binding doc] Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Stephen Warren 提交于
The Tegra20 CAR (Clock And Reset) Controller controls most aspects of most clocks within Tegra20. The device tree binding models this as a single monolithic clock provider, which exports many clocks. This reduces the number of nodes needed in device tree to represent these clocks. This binding is only useful for Tegra20; the set of clocks that exists on Tegra30 is sufficiently different to merit its own binding. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NSimon Glass <sjg@chromium.org> [pgaikwad: Added mux clk ids and sorted CAR node] Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 25 1月, 2013 1 次提交
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由 Fabio Estevam 提交于
Similarly as it was done for mx6q, use a DT lookup in order to make maintainance task for the clock devices easier. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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- 19 1月, 2013 1 次提交
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由 Barry Song 提交于
this patche deletes hard code that registers clkdev by things like: clk_register_clkdev(clk, NULL, "b0030000.nand"); clk_register_clkdev(clk, NULL, "b0040000.audio"); clk_register_clkdev(clk, NULL, "b0080000.usp"); prima2 clock controller becomes a clock provider and every dt node just declares its clock sources by dt prop. it also makes us easier to extend this driver to support both prima2 and marco as marco has different address mapping with prima2. Signed-off-by: NBarry Song <Baohua.Song@csr.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 04 1月, 2013 1 次提交
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由 Fabio Estevam 提交于
'clock-output-names' is not used in any of the dts/dtsi files for i.mx. Remove it from the examples, so that the example and the real usage in the dtsi files can match. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Acked-by: NRob Herring <rob.herring@calxeda.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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- 22 11月, 2012 3 次提交
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由 Sascha Hauer 提交于
In current code the ethernet PLL is not handled correctly. The PLL runs at 500MHz and has different outputs. Only the enet reference clock is implemented. This patch changes the PLL so that it outputs 500MHz and adds the additional outputs as dividers. This now matches the datasheet which says: > This PLL synthesizes a low jitter clock from 24 MHz reference clock. > The PLL outputs a 500 MHz clock. The reference clocks generated by this PLL are: > • Ref_PCIe = 125 MHz > • Ref_SATA = 100 MHz > • Ref_ethernet, which is configurable based on the PLL_ENET[1:0] register field. Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Acked-by: NShawn Guo <shawn.guo@linaro.org>
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由 Sascha Hauer 提交于
In recent reference manuals the PLLs were renumbered. PLL8 now is PLL6 and vice versa. Change the code according to the reference manual to avoid confusion. Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Acked-by: NShawn Guo <shawn.guo@linaro.org>
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由 Fabio Estevam 提交于
Similarly as it was done for mx6q, use a DT lookup in order to make maintainance task for the clock devices easier. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Acked-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
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- 20 11月, 2012 4 次提交
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由 Gregory CLEMENT 提交于
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
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由 Sebastian Hesselbarth 提交于
This driver allows to provide DT clocks for clock gates found on Marvell Dove and Kirkwood SoCs. The clock gates are referenced by the phandle index of the corresponding bit in the clock gating control register to ease lookup in the datasheet. Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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由 Gregory CLEMENT 提交于
Add Armada 370/XP specific CPU clocks Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
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由 Sebastian Hesselbarth 提交于
This driver allows to provide DT clocks for core clocks found on Marvell Kirkwood, Dove & 370/XP SoCs. The core clock frequencies and ratios are determined by decoding the Sample-At-Reset registers. Although technically correct, using a divider of 0 will lead to div_by_zero panic. Let's use a ratio of 0/1 instead to fail later with a zero clock. Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Tested-by Gregory CLEMENT <gregory.clement@free-electrons.com>
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- 17 11月, 2012 1 次提交
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由 Fabio Estevam 提交于
Use a better name for the USB PHY clock. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 14 11月, 2012 1 次提交
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由 Josh Cartwright 提交于
Provide simplified models for the necessary clocks on the zynq-7000 platform. Currently, the PLLs, the CPU clock network, and the basic peripheral clock networks (for SDIO, SMC, SPI, QSPI, UART) are modelled. OF bindings are also provided and documented. Signed-off-by: NJosh Cartwright <josh.cartwright@ni.com> Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: NMike Turquette <mturquette@linaro.org> Acked-by: NMichal Simek <michal.simek@xilinx.com>
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- 12 11月, 2012 1 次提交
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由 Sascha Hauer 提交于
This adds a i.MX25 dtsi file along with the i.MX25 clock tree documentation. The devicetree should be fairly complete for: - uart - fec - i2c - spi - pwm - nand - gpio - wdog - esdhc - flexcan The more exotic devices currently miss clock bindings. Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Acked-by: NShawn Guo <shawn.guo@linaro.org>
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- 21 9月, 2012 1 次提交
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由 Tony Prisk 提交于
Bindings for gpio, interrupt controller, power management controller, timer, realtime clock, serial uart, ehci and uhci controllers and framebuffer controllers used on the arch-vt8500 platform. Framebuffer binding also specifies a 'display' node which is required for determining the lcd panel data. Signed-off-by: NTony Prisk <linux@prisktech.co.nz>
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- 11 9月, 2012 3 次提交
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由 Shawn Guo 提交于
It really becomes an maintenance issue that every time a device needs to look up (clk_get) a clock we have to patch kernel clock file to call clk_register_clkdev for that clock. Since clock DT support which is meant to resolve clock lookup in device tree is in place, the patch moves imx6q client devices' clock lookup over to device tree, so that any new lookup to be added at later time can just get done in DT instead of kernel. Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Shawn Guo 提交于
It really becomes a maintenance issue that every time a device needs to look up (clk_get) a clock we have to patch kernel clock file to call clk_register_clkdev for that clock. Since clock DT support which is meant to resolve clock lookup in device tree is in place, the patch moves imx23 client devices' clock lookup over to device tree, so that any new lookup to be added at later time can just get done in DT instead of kernel. Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Shawn Guo 提交于
It really becomes a maintenance issue that every time a device needs to look up (clk_get) a clock we have to patch kernel clock file to call clk_register_clkdev for that clock. Since clock DT support which is meant to resolve clock lookup in device tree is in place, the patch moves imx28 client devices' clock lookup over to device tree, so that any new lookup to be added at later time can just get done in DT instead of kernel. Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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- 12 7月, 2012 2 次提交
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由 Rob Herring 提交于
This adds real clock support to Calxeda Highbank SOC using the common clock infrastructure. Signed-off-by: NRob Herring <rob.herring@calxeda.com> [mturquette@linaro.org: fixed up invalid writes to const struct member] Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Grant Likely 提交于
Based on work 1st by Ben Herrenschmidt and Jeremy Kerr, then by Grant Likely, this patch adds support to clk_get to allow drivers to retrieve clock data from the device tree. Platforms scan for clocks in DT with of_clk_init and a match table, and the register a provider through of_clk_add_provider. The provider's clk_src_get function will be called when a device references the provider's OF node for a clock reference. v6 (Rob Herring): - Return error values instead of NULL to match clock framework expectations v5 (Rob Herring): - Move from drivers/of into common clock subsystem - Squashed "dt/clock: add a simple provider get function" and "dt/clock: add function to get parent clock name" - Rebase to 3.4-rc1 - Drop CONFIG_OF_CLOCK and just use CONFIG_OF - Add missing EXPORT_SYMBOL to various functions - s/clock-output-name/clock-output-names/ - Define that fixed-clock binding is a single output v4 (Rob Herring): - Rework for common clk subsystem - Add of_clk_get_parent_name function v3: - Clarified documentation v2: - fixed errant ';' causing compile error - Editorial fixes from Shawn Guo - merged in adding lookup to clkdev - changed property names to match established convention. After working with the binding a bit it really made more sense to follow the lead of 'reg', 'gpios' and 'interrupts' by making the input simply 'clocks' & 'clock-names' instead of 'clock-input-*', and to only use clock-output* for the producer nodes. (Sorry Shawn, this will mean you need to change some code, but it should be trivial) - Add ability to inherit clocks from parent nodes by using an empty 'clock-ranges' property. Useful for busses. I could use some feedback on the new property name, 'clock-ranges' doesn't feel right to me. Signed-off-by: NGrant Likely <grant.likely@secretlab.ca> Signed-off-by: NRob Herring <rob.herring@calxeda.com> Reviewed-by: NShawn Guo <shawn.guo@freescale.com> Cc: Sascha Hauer <kernel@pengutronix.de> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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