- 17 8月, 2013 3 次提交
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由 Mike Turquette 提交于
These registration calls may be used by loadable modules. Export them. Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Fabio Estevam 提交于
clk_register_divider() needs to be exported so that it could be used in a module driver, otherwise we get the following error: ERROR: "clk_register_divider" [sound/soc/mxs/snd-soc-mxs.ko] undefined! Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NMike Turquette <mturquette@linaro.org> [mturquette@linaro.org: also export clk_register_divider_table]
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由 Stephen Boyd 提交于
Export this symbol so that modules can register fixed rate clocks. Signed-off-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 09 8月, 2013 16 次提交
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由 Sachin Kamat 提交于
__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Tested-by: NStephen Warren <swarren@nvidia.com> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
__initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Yadwinder Singh Brar 提交于
This patch adds support to register three(AP/CP/BT) buffered 32.768 KHz outputs of mfd-s2mps11 with common clock framework. Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
'exynos5420_plls' is used only in this file. Make is static. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
exynos5250_plls is used only in this file. Make it static. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
'exynos4_plls' is used only in this file. Make it static. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Fabio Estevam 提交于
Fix the following sparse warning: drivers/clk/mxs/clk-imx23.c:102:12: warning: symbol 'mx23_clocks_init' was not declared. Should it be static? Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Acked-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Axel Lin 提交于
clk_register_composite() and clk_register_factors() return ERR_PTR on error. Signed-off-by: NAxel Lin <axel.lin@ingics.com> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Mike Turquette 提交于
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由 Sachin Kamat 提交于
Fixes a trivial typo. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 06 8月, 2013 3 次提交
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由 Tomasz Figa 提交于
This patch adds new, Common Clock Framework-based clock driver for Samsung S3C64xx SoCs. The driver is just added, without actually letting the platforms use it yet, since this requires more intermediate steps. Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Tomasz Figa 提交于
This patch adds support for PLL6552 and PLL6553 PLLs present on Samsung S3C64xx SoCs. Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Tomasz Figa 提交于
Some platforms have read-only clock muxes that are preconfigured at reset and cannot be changed at runtime. This patch extends mux clock driver to allow handling such read-only muxes by adding new CLK_MUX_READ_ONLY mux flag. Signed-off-by: NTomasz Figa <tomasz.figa@gmail.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 03 8月, 2013 11 次提交
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由 Vikas Sajjan 提交于
Adds the EPLL and VPLL freq table for exynos5250 SoC. Signed-off-by: NVikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Vikas Sajjan 提交于
While trying to get rate of "mout_vpllsrc" MUX (parent) for registering the "fout_vpll" (child), we found get rate was failing. So this patch moves the mout_vpllsrc MUX out of the existing common list and registers the mout_vpllsrc MUX before the PLL registrations. Reviewed-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NVikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Vikas Sajjan 提交于
This patch adds set_rate and round_rate clk_ops for PLL36xx Reviewed-by: NTomasz Figa <t.figa@samsung.com> Reviewed-by: NDoug Anderson <dianders@chromium.org> Signed-off-by: NVikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Yadwinder Singh Brar 提交于
This patch add set_rate() and round_rate() for PLL35xx Reviewed-by: NDoug Anderson <dianders@chromium.org> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Yadwinder Singh Brar 提交于
This patch defines a common rate_table which will contain recommended p, m, s, k values for supported rates that needs to be changed for changing corresponding PLL's rate. Reviewed-by: NDoug Anderson <dianders@chromium.org> Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Yadwinder Singh Brar 提交于
This patch removes samsung_clk_register_pll35xx() and samsung_clk_register_pll36xx() registaration functions as users migrated to new samsung_clk_register_pll(). Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Yadwinder Singh Brar 提交于
This patch migrates exynos5420 pll registeration to use common samsung_clk_register_pll() by intialising table of PLLs and adding PLLs to unique id list of clocks. Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NVikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Yadwinder Singh Brar 提交于
This patch migrates exynos4 pll registeration to use common samsung_clk_register_pll() by intialising table of PLLs. Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NVikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Yadwinder Singh Brar 提交于
This patch migrates exynos5250 pll registeration to use common samsung_clk_register_pll() by intialising table of PLLs and adding PLLs to unique id list of clocks. Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NVikas Sajjan <vikas.sajjan@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Yadwinder Singh Brar 提交于
This patch defines a common samsung_clk_register_pll() Since pll2550 & pll35xx and pll2650 & pll36xx have exactly same clk ops implementation, added pll2550 and pll2650 also. Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Yadwinder Singh Brar 提交于
This patch unifies clk strutures used for PLL35xx & PLL36xx and adding an extra member lock_reg, so that common code can be factored out. Reviewed-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 31 7月, 2013 5 次提交
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由 Sachin Kamat 提交于
Exynos5250 G2D IP requires only the gate clock. Update the binding documentation accordingly. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Cc: Inki Dae <inki.dae@samsung.com> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sachin Kamat 提交于
Added clock entries for thermal management unit (TMU) for Exynos4 SoCs. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Rahul Sharma 提交于
hdmi driver needs hdmiphy clock which is one of the parent for hdmi mux clock. This is required while changing the parent of mux clock. Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Rahul Sharma 提交于
hdmi driver needs to change the parent of hdmi clock frequently between pixel clock and hdmiphy clock. hdmiphy is not stable after power on and for a short interval while changing the phy configuration. For this duration pixel clock is used to clock hdmi. This patch is exposing the mux for changing parent. Signed-off-by: NRahul Sharma <rahul.sharma@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Tushar Behera 提交于
commit 79d743c1 ("clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2") added two new clock entries. Add the clock entry enum numbers to documentation. Signed-off-by: NTushar Behera <tushar.behera@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 30 7月, 2013 1 次提交
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由 Sachin Kamat 提交于
Adds gate clock for G2D IP for Exynos5250 SoC. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 26 7月, 2013 1 次提交
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由 Sachin Kamat 提交于
exynos_audss_clk_init() is used only in this file. Make it static. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Acked-by: NKukjin Kim <kgene.kim@samsung.com> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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