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  1. 18 6月, 2008 1 次提交
    • J
      powerpc/4xx: Workaround for PPC440EPx/GRx PCI_28 Errata · 5ce4b596
      由 Josh Boyer 提交于 
      The 440EPx/GRx chips don't support PCI MRM commands.  Drivers determine this
by looking for a zero value in the PCI cache line size register.  However,
some drivers write to this register upon initialization.  This can cause
MRMs to be used on these chips, which may cause deadlocks on PLB4.

The workaround implemented here introduces a new indirect_type flag, called
PPC_INDIRECT_TYPE_BROKEN_MRM.  This is set in the pci_controller structure in
the pci fixup function for 4xx PCI bridges by determining if the bridge is
compatible with 440EPx/GRx.  The flag is checked in the indirect_write_config
function, and forces any writes to the PCI_CACHE_LINE_SIZE register to be
zero, which will disable MRMs for these chips.

A similar workaround has been tested by AMCC on various PCI cards, such as
the Silicon Image ATA card and Intel E1000 GIGE card.  Hangs were seen with
the Silicon Image card, and MRMs were seen on the bus with a PCI analyzer.
With the workaround in place, the card functioned properly and only Memory
Reads were seen on the bus with the analyzer.
Acked-by: NStefan Roese <sr@denx.de>
Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
      5ce4b596
  3. 18 4月, 2008 1 次提交
  5. 24 1月, 2008 1 次提交
  7. 17 1月, 2008 3 次提交
  9. 21 12月, 2007 1 次提交
  11. 20 12月, 2007 3 次提交
  13. 11 12月, 2007 4 次提交
  15. 19 11月, 2007 1 次提交
  17. 12 10月, 2007 1 次提交
  19. 26 7月, 2007 1 次提交
  21. 24 7月, 2007 2 次提交
  23. 23 7月, 2007 3 次提交
  25. 29 6月, 2007 7 次提交
  27. 14 6月, 2007 3 次提交
    • B
      [POWERPC] Rewrite IO allocation & mapping on powerpc64 · 3d5134ee
      由 Benjamin Herrenschmidt 提交于 
      This rewrites pretty much from scratch the handling of MMIO and PIO
space allocations on powerpc64.  The main goals are:

 - Get rid of imalloc and use more common code where possible
 - Simplify the current mess so that PIO space is allocated and
   mapped in a single place for PCI bridges
 - Handle allocation constraints of PIO for all bridges including
   hot plugged ones within the 2GB space reserved for IO ports,
   so that devices on hotplugged busses will now work with drivers
   that assume IO ports fit in an int.
 - Cleanup and separate tracking of the ISA space in the reserved
   low 64K of IO space. No ISA -> Nothing mapped there.

I booted a cell blade with IDE on PIO and MMIO and a dual G5 so
far, that's it :-)

With this patch, all allocations are done using the code in
mm/vmalloc.c, though we use the low level __get_vm_area with
explicit start/stop constraints in order to manage separate
areas for vmalloc/vmap, ioremap, and PCI IOs.

This greatly simplifies a lot of things, as you can see in the
diffstat of that patch :-)

A new pair of functions pcibios_map/unmap_io_space() now replace
all of the previous code that used to manipulate PCI IOs space.
The allocation is done at mapping time, which is now called from
scan_phb's, just before the devices are probed (instead of after,
which is by itself a bug fix). The only other caller is the PCI
hotplug code for hot adding PCI-PCI bridges (slots).

imalloc is gone, as is the "sub-allocation" thing, but I do beleive
that hotplug should still work in the sense that the space allocation
is always done by the PHB, but if you unmap a child bus of this PHB
(which seems to be possible), then the code should properly tear
down all the HPTE mappings for that area of the PHB allocated IO space.

I now always reserve the first 64K of IO space for the bridge with
the ISA bus on it. I have moved the code for tracking ISA in a separate
file which should also make it smarter if we ever are capable of
hot unplugging or re-plugging an ISA bridge.

This should have a side effect on platforms like powermac where VGA IOs
will no longer work. This is done on purpose though as they would have
worked semi-randomly before. The idea at this point is to isolate drivers
that might need to access those and fix them by providing a proper
function to obtain an offset to the legacy IOs of a given bus.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NPaul Mackerras <paulus@samba.org>
      3d5134ee
    • L
      [POWERPC] Show EEH per-device false positives · 858955bd
      由 Linas Vepstas 提交于 
      Track and report the number of times we read an all-1s value (0xff,
0xffff or 0xffffffff) from each device which is valid data, not
indicating EEH isolation.
Signed-off-by: NLinas Vepstas <linas@austin.ibm.com>

----
 arch/powerpc/platforms/pseries/eeh.c       |    5 +++++
 arch/powerpc/platforms/pseries/eeh_sysfs.c |    3 +++
 include/asm-powerpc/pci-bridge.h           |    1 +
 3 files changed, 9 insertions(+)
Signed-off-by: NPaul Mackerras <paulus@samba.org>
      858955bd
    • L
      [POWERPC] pseries: asm/pci-bridge.h CONFIG_ minor cleanup · c2e221e8
      由 Linas Vepstas 提交于 
      Use the correct CONFIG_ option to mark off the EEH bits.
Move the EEH bits to the bottom of the struct.
The config_space array is used by EEH only; it does not
need to be part of the struct for non-pseries machines.
Signed-off-by: NLinas Vepstas <linas@austin.ibm.com>

----
Revised patch, per commments from Michael Ellerman.

 include/asm-powerpc/pci-bridge.h |   16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)
Signed-off-by: NPaul Mackerras <paulus@samba.org>
      c2e221e8
  29. 24 1月, 2007 1 次提交
  31. 08 12月, 2006 1 次提交
    • B
      [POWERPC] Fix mmap of PCI resource with hack for X · 396a1a58
      由 Benjamin Herrenschmidt 提交于 
      The powerpc version of pci_resource_to_user() and associated hooks
used by /proc/bus/pci and /sys/bus/pci mmap have been broken for some
time on machines that don't have a 1:1 mapping of devices (basically
on non-PowerMacs) and have PCI devices above 32 bits.

This attempts to fix it as well as possible.

The rule is supposed to be that pci_resource_to_user() always converts
the resources back into a BAR values since that's what the /proc
interface was supposed to deal with. However, for X to work on
platforms where PCI MMIO is not mapped 1:1, it became a habit of
platforms like powerpc to pass "fixed up" values there since X expects
to be able to use values from /proc/bus/pci/devices as offsets to mmap
of /dev/mem...

So we keep that contraption here, causing also /sys/*/resource to
expose fully absolute MMIO addresses instead of BAR values, which is
ugly, but should still work as long as those are only used to calculate
alignment within a page.

X is still broken when built 32 bits on machines where PCI MMIO can be
above 32-bit space unfortunately.
Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: NPaul Mackerras <paulus@samba.org>
      396a1a58
  33. 04 12月, 2006 1 次提交
  35. 04 10月, 2006 1 次提交
  37. 15 6月, 2006 1 次提交
  39. 24 5月, 2006 3 次提交