From: Imre Deak <imre.deak@nokia.com>

Recently the UP versions of these functions were refactored and as
a side effect it became possible to call them for the current thread.
This isn't true for the SMP versions however, so fix this up.
Signed-off-by: NImre Deak <imre.deak@nokia.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The VIVT cache of a highmem page is always flushed before the page
is unmapped.  This cache flush is explicit through flush_cache_kmaps()
in flush_all_zero_pkmaps(), or through __cpuc_flush_dcache_area() in
kunmap_atomic().  There is also an implicit flush of those highmem pages
that were part of a process that just terminated making those pages free
as the whole VIVT cache has to be flushed on every task switch. Hence
unmapped highmem pages need no cache maintenance in that case.

However unmapped pages may still be cached with a VIPT cache because the
cache is tagged with physical addresses.  There is no need for a whole
cache flush during task switching for that reason, and despite the
explicit cache flushes in flush_all_zero_pkmaps() and kunmap_atomic(),
some highmem pages that were mapped in user space end up still cached
even when they become unmapped.

So, we do have to perform cache maintenance on those unmapped highmem
pages in the context of DMA when using a VIPT cache.  Unfortunately,
it is not possible to perform that cache maintenance using physical
addresses as all the L1 cache maintenance coprocessor functions accept
virtual addresses only.  Therefore we have no choice but to set up a
temporary virtual mapping for that purpose.

And of course the explicit cache flushing when unmapping a highmem page
on a system with a VIPT cache now can go, which should increase
performance.

While at it, because the code in __flush_dcache_page() has to be modified
anyway, let's also make sure the mapped highmem pages are pinned with
kmap_high_get() for the duration of the cache maintenance operation.
Because kunmap() does unmap highmem pages lazily, it was reported by
Gary King <GKing@nvidia.com> that those pages ended up being unmapped
during cache maintenance on SMP causing segmentation faults.
Signed-off-by: NNicolas Pitre <nico@marvell.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

From: Julien Langer <julien.langer@gmail.com>

AT91: when turning off the PLLs during suspend, don't wait for the lock
flag to be set. Previously the code would always run into the loop
limitation of 1000 iterations because the flag is never set when turning
the PLLs off.

Comments from Anders Larsen:

 (in http://marc.info/?l=linux-kernel&m=127058929724193&w=2)
Signed-off-by: NJulien Langer <julien.langer@gmail.com>
Signed-off-by: NAnders Larsen <al@alarsen.net>
Acked-by: NAndrew Victor <linux@maxim.org.za>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Write combining/cached device mappings are not setting the shared bit,
which could potentially cause problems on SMP systems since the cache
lines won't participate in the cache coherency protocol.
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Tested-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>

at91 slow-clock resume: Don't wait for a disabled PLL to lock.

We run into this problem with the PLLB on the at91: ohci-at91 disables
the PLLB when going to suspend. The slowclock code however tries to do
the same: It saves the PLLB register value and when restoring the value
during resume, it waits for the PLLB to lock again. However the PLL will
never lock and the loop would run into its timeout because the slowclock
code just stored and restored an empty register.
This fixes the problem by only restoring PLLA/PLLB when they were enabled
at suspend time.

Cc: Andrew Victor <avictor.za@gmail.com>
Signed-off-by: NAnders Larsen <al@alarsen.net>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

98e12b5a ("ARM: Fix decompressor's kernel size estimation for
ROM=y") broke the Thumb-2 decompressor because it added an entry in the
LC0 table but didn't adjust the offset the Thumb-2 code uses to load the
SP from that table.  Fix it.

Cc: stable <stable@kernel.org>
Signed-off-by: NRabin Vincent <rabin@rab.in>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The functions ep93xx_gpio_update_int_params and ep93xx_gpio_int_mask
are not exported and should be static.  This was overlooked when
moving the code from core.c.

Also, change a comment to better indicate what the code is for.
Signed-off-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Acked-by: NRyan Mallon <ryan@bluewatersys.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Added missing down on the memMap->lock semaphore. Also fixed a return
statement so that we always exit with an up (i.e. early exit via return
is not allowed)
Signed-off-by: NLeo Hao Chen <leochen@broadcom.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This hushes the following warning:

arch/arm/mach-davinci/include/mach/da8xx.h:104: warning: ‘struct platform_device’
declared inside parameter list
arch/arm/mach-davinci/include/mach/da8xx.h:104: warning: its scope is only this
definition or declaration, which is probably not what you want
Signed-off-by: NSergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

IRQ 29 has two possible interrupts DDRINT and RTC, but having both in
the default priority table is confusing (and triggers a warning from
sparse.)

This patch removes the lower priority DDRINT from the default priority
table leaving the RTC setting as the default.
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch fixes an issue where a DMA channel can erroneously process an
event generated by a previous transfer.  A failure case is where DMA is
being used for SPI transmit and receive channels on OMAP L138.  In this
case there is a single bit that controls all event generation from the
SPI peripheral.  Therefore it is possible that between when edma_stop()
has been called for the transmit channel on a previous transfer and
edma_start() is called for the transmit channel on a subsequent transfer,
that a transmit event has been generated.

The fix is to clear events in edma_start().  This prevents false events
from being processed when events are enabled for that channel.
Signed-off-by: NBrian Niebuhr <bniebuhr@efjohnson.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

The da8xx/omap-l1 boards refuse to build when CONFIG_DAVINCI_MUX is undefined
because arch/arm/mach-davinci/mux.c:da8xx_pinmux_setup() is not defined.

This patch fixes this issue. This is build tested with davinci_all_defconfig
and da8xx_omapl_defconfig and boot tested on DA830 EVM.
Reported-by: NShanmuga Sundaram Mahendran <shanmuga@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

On da830, when the same timer is used for clocksource and clockevent,
the timer can be started before the clockevent is
registered/initialzed.  This creates a window where a timer
interrupt might fire before the clockevent handler has been
setup and causes a crash.

This patch moves the actual enable/start of the timer after
the clockevent has ben registered.
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h

percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files.  percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.

percpu.h -> slab.h dependency is about to be removed.  Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability.  As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.

  http://userweb.kernel.org/~tj/misc/slabh-sweep.py

The script does the followings.

* Scan files for gfp and slab usages and update includes such that
  only the necessary includes are there.  ie. if only gfp is used,
  gfp.h, if slab is used, slab.h.

* When the script inserts a new include, it looks at the include
  blocks and try to put the new include such that its order conforms
  to its surrounding.  It's put in the include block which contains
  core kernel includes, in the same order that the rest are ordered -
  alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
  doesn't seem to be any matching order.

* If the script can't find a place to put a new include (mostly
  because the file doesn't have fitting include block), it prints out
  an error message indicating which .h file needs to be added to the
  file.

The conversion was done in the following steps.

1. The initial automatic conversion of all .c files updated slightly
   over 4000 files, deleting around 700 includes and adding ~480 gfp.h
   and ~3000 slab.h inclusions.  The script emitted errors for ~400
   files.

2. Each error was manually checked.  Some didn't need the inclusion,
   some needed manual addition while adding it to implementation .h or
   embedding .c file was more appropriate for others.  This step added
   inclusions to around 150 files.

3. The script was run again and the output was compared to the edits
   from #2 to make sure no file was left behind.

4. Several build tests were done and a couple of problems were fixed.
   e.g. lib/decompress_*.c used malloc/free() wrappers around slab
   APIs requiring slab.h to be added manually.

5. The script was run on all .h files but without automatically
   editing them as sprinkling gfp.h and slab.h inclusions around .h
   files could easily lead to inclusion dependency hell.  Most gfp.h
   inclusion directives were ignored as stuff from gfp.h was usually
   wildly available and often used in preprocessor macros.  Each
   slab.h inclusion directive was examined and added manually as
   necessary.

6. percpu.h was updated not to include slab.h.

7. Build test were done on the following configurations and failures
   were fixed.  CONFIG_GCOV_KERNEL was turned off for all tests (as my
   distributed build env didn't work with gcov compiles) and a few
   more options had to be turned off depending on archs to make things
   build (like ipr on powerpc/64 which failed due to missing writeq).

   * x86 and x86_64 UP and SMP allmodconfig and a custom test config.
   * powerpc and powerpc64 SMP allmodconfig
   * sparc and sparc64 SMP allmodconfig
   * ia64 SMP allmodconfig
   * s390 SMP allmodconfig
   * alpha SMP allmodconfig
   * um on x86_64 SMP allmodconfig

8. percpu.h modifications were reverted so that it could be applied as
   a separate patch and serve as bisection point.

Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: NTejun Heo <tj@kernel.org>
Guess-its-ok-by: NChristoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>

This add USB Host capability. The Armadillo 500 board is supplied
with two USB Host connectors driven by the USB OTG and USB Host 2
ports, through two NXP isp 1504 transceivers.
Signed-off-by: NAlberto Panizzo <maramaopercheseimorto@gmail.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

arch/arm/mach-mx3/mx31lite-db.c: linux/platform_device.h is included more than once.
Signed-off-by: NAndrea Gelmini <andrea.gelmini@gelma.net>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

arch/arm/mach-mx3/mach-pcm037.c: linux/fsl_devices.h is included more than once.
Signed-off-by: NAndrea Gelmini <andrea.gelmini@gelma.net>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

This patch adds support for SoC build-in watchdog device on litekit
board.
Signed-off-by: NVladimir Zapolskiy <vzapolskiy@gmail.com>
Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

This patch adds support for build-in watchdog device found on
Freescale imx31 and imx35 SoCs.
Signed-off-by: NVladimir Zapolskiy <vzapolskiy@gmail.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

When compiling the kernel to Thumb-2, using a 16-bit NOP in the
memmove() implementation causes the preceding ADD PC instruction to
branch incorrectly in the middle of a 32-bit LDR or STR instruction. The
memmove() code is now similar to the memcpy() template.
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Current implementation of jprobes allocates empty pt_regs from the
stack which is then passed to kprobe_handler() and eventually to
singlestep().  Now when instruction being simulated is STMFD (like
in normal function prologues without CONFIG_FRAME_POINTER), stores
using SP actually write over top of the fabricated pt_regs
structure.

This can be reproduced for example by using LKDTM module:
    # modprobe lkdtm
    # mount -t debugfs none /sys/kernel/debug
    # echo PANIC > /sys/kernel/debug/provoke-crash/INT_HW_IRQ_EN

after this, it fails with corrupted registers (before the requested crash would occur):

lkdtm: Crash point INT_HW_IRQ_EN of type PANIC hit, trigger in 9 rounds
lkdtm: Crash point INT_HW_IRQ_EN of type PANIC hit, trigger in 8 rounds
Internal error: Oops - undefined instruction: 0 [#1]
last sysfs file: /sys/devices/platform/serial8250.0/sleep_timeout
Modules linked in: lkdtm
CPU: 0    Not tainted  (2.6.34-rc2 #69)
PC is at irq_desc+0x1638/0xeeb0
LR is at 0x25
pc : [<c050b428>]    lr : [<00000025>]    psr: c80a0013
sp : ce94bd60  ip : c050b3e8  fp : a0000013
r10: c0aa453c  r9 : cf5d4000  r8 : ce9a1822
r7 : c050b424  r6 : 00000025  r5 : c039d8f8  r4 : c050b3e8
r3 : 00000001  r2 : cf4d0440  r1 : c039d8f8  r0 : 00000020
Flags: NZcv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
Control: 10c5387d  Table: 8e804019  DAC: 00000015
Process sh (pid: 496, stack limit = 0xce94a2e8)
Stack: (0xce94bd60 to 0xce94c000)
[...]
Code: 000002cd 00000000 00000000 00000001 (dead4ead)
---[ end trace 2b46d5f2b682f370 ]---
Kernel panic - not syncing: Fatal exception in interrupt

This patch allocates enough space (2 * sizeof(struct pt_regs)) from
the stack to prevent such corruption.
Signed-off-by: NMika Westerberg <ext-mika.1.westerberg@nokia.com>
Acked-by: NNicolas Pitre <nico@marvell.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

clkdev.h is using struct device *. Due to this compilation
warning is comming. Removing this warning.
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

irq.h is using struct pt_regs *. Due to this compilation
warning is comming. Removing this warning by adding declaration
of struct pt_regs.
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

A CPU has VFPv3 hardware if the FPSID[19:16] bits are 2 or more.
Currently Linux was only checking for 3 or more.
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The mandatory barriers (mb, rmb, wmb) are used even on uniprocessor
systems for things like ordering Normal Non-cacheable memory accesses
with DMA transfer (via Device memory writes). The current implementation
uses dmb() for mb() and friends but this is not sufficient. The DMB only
ensures the relative ordering of the observability of accesses by other
processors or devices acting as masters. In case of DMA transfers
started by writes to device memory, the relative ordering is not ensured
because accesses to slave ports of a device are not considered
observable by the DMB definition.

A DSB is required for the data to reach the main memory (even if mapped
as Normal Non-cacheable) before the device receives the notification to
begin the transfer. Furthermore, some L2 cache controllers (like L2x0 or
PL310) buffer stores to Normal Non-cacheable memory and this would need
to be drained with the outer_sync() function call.

The patch also allows platforms to define their own mandatory barriers
implementation by selecting CONFIG_ARCH_HAS_BARRIERS and providing a
mach/barriers.h file.

Note that the SMP barriers are unchanged (being DMBs as before) since
they are only guaranteed to work with Normal Cacheable memory.
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

The L2x0 cache controllers need to explicitly drain their write buffer
even for Normal Noncacheable memory accesses.
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This patch introduces the outer_cache_fns.sync function pointer together
with the OUTER_CACHE_SYNC config option that can be used to drain the
write buffer of the outer cache.
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

To avoid #include collisions with subsequent patches in the series, this
patch moves the outer_cache definitions to a separate asm/outercache.h
file.
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Power Gates must to be always enabled.
Signed-off-by: NAlberto Panizzo <maramaopercheseimorto@gmail.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: NAlberto Panizzo <maramaopercheseimorto@gmail.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Since the using of Bad Block Table is not constantly a good behave
I had made it configurable.
Signed-off-by: NAlberto Panizzo <maramaopercheseimorto@gmail.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: NAlberto Panizzo <maramaopercheseimorto@gmail.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

According to imx31 reference manual the signal from external low
frequency clock is sent to RTC clock.
The patch makes redundant the previously defined mxc_rtc clock.
Signed-off-by: NVladimir Zapolskiy <vzapolskiy@gmail.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Daniel Mack <daniel@caiaq.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

"Input: add KEY_WPS_BUTTON definition" introduced
a generic keycode for WPS input events.
Signed-off-by: NChristian Lamparter <chunkeey@googlemail.com>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

Commit "Input: add KEY_WPS_BUTTON definition"
added a generic keycode for WPS button.
Let's use it, instead of "F1" mapping.
Signed-off-by: NChristian Lamparter <chunkeey@googlemail.com>
Signed-off-by: NNicolas Pitre <nico@marvell.com>

This fixes a warning when booting 2.6.34-rc2:

[   26.619814] ------------[ cut here ]------------
[   26.624604] WARNING: at fs/proc/generic.c:316 __xlate_proc_name+0xac/0xc0()
[   26.631555] name 'on/off button'
[   26.634753] Modules linked in:
Signed-off-by: NDaniel Mack <daniel@caiaq.de>
Cc: Sven Neumann <s.neumann@raumfeld.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

Remove duplicated #include('s) in
 arch/arm/mach-pxa/raumfeld.c
Signed-off-by: NHuang Weiyi <weiyi.huang@gmail.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

The function locomo_m62332_senddata sends a three byte i2c message to
a M62332 DAC. This entire function is guarded with a spin_lock_irqsave
at the start of the function and a spin_unlock_irqrestore at the end.

As each byte is transferred, the i2c ACK from the DAC is checked.
Currently, if the ACK is missing the function simply returns without
the unlock. It also leaves the i2c bus in an invalid state since the
last byte transferred did not have a "stop" condition and leave the
bus idle.

Fix this by adding an exit path using goto.
Signed-off-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

The locomo spi registers are all defined in locomo.h as offsets
from the first spi register LOCOMO_SPI (0x60), which is itself
an offset from the locomo base address.  To correctly access
these registers LOCOMO_SPI must always be included in the
address calculation.

There are two places in locomo.c where this is not done.  The
first one, in locomo_suspend, actually results in a write to
LOCOMO_ST instead of LOCOMO_SPICT.  The second is in __locomo_probe
and results in a write to LOCOMO_MCSX2 instead of LOCOMO_SPIIE.

Fix these by including LOCOMO_SPI in the calculation.
Signed-off-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>

sharpsl_pm.c actually depends on max1111 driver being built-in when
not using legacy ssp code.
Reported-by: NJonathan Cameron <jic23@cam.ac.uk>
Signed-off-by: NEric Miao <eric.y.miao@gmail.com>