1. 09 11月, 2013 4 次提交
  2. 08 11月, 2013 1 次提交
    • B
      drm/i915/bdw: Handle forcewake for writes on gen8 · ab2aa47e
      Ben Widawsky 提交于
      GEN8 removes the GT FIFO which we've all come to know and love. Instead
      it offers a wider range of optimized registers which always keep a
      shadowed copy, and are fed to the GPU when it wakes.
      
      How this is implemented in hardware is still somewhat of a mystery. As
      far as I can tell, the basic design is as follows:
      
      If the register is not optimized, you must use the old forcewake
      mechanism to bring the GT out of sleep. [1]
      
      If register is in the optimized list the write will signal that the
      GT should begin to come out of whatever sleep state it is in.
      
      While the GT is coming out of sleep, the requested write will be stored
      in an intermediate shadow register.
      
      Do to the fact that the implementation details are not clear, I see
      several risks:
      1. Order is not preserved as it is with GT FIFO. If we issue multiple
      writes to optimized registers, where order matters, we may need to
      serialize it with forcewake.
      2. The optimized registers have only 1 shadowed slot, meaning if we
      issue multiple writes to the same register, and those values need to
      reach the GPU in order, forcewake will be required.
      
      [1] We could implement a SW queue the way the GT FIFO used to work if
      desired.
      
      NOTE: Compile tested only until we get real silicon.
      
      v2:
      - Use a default case to make future platforms also work.
      - Get rid of IS_BROADWELL since that's not yet defined, but we want to
        MMIO as soon as possible.
      
      v3: Apply suggestions from Mika's review:
      - s/optimized/shadowed/
      - invert the logic of the helper so that it does what it says (the
        code itself was correct, just confusing to read).
      
      v4:
      - Squash in lost break.
      
      Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1)
      Reviewed-by: NMika Kuoppala <mika.kuoppala@intel.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      ab2aa47e
  3. 05 11月, 2013 1 次提交
  4. 02 11月, 2013 18 次提交
  5. 01 11月, 2013 3 次提交
  6. 31 10月, 2013 9 次提交
  7. 30 10月, 2013 4 次提交