1. 24 2月, 2012 4 次提交
    • B
      PCI: add struct pci_host_bridge and a list of all bridges found · 5a21d70d
      Bjorn Helgaas 提交于
      This adds a list of all PCI host bridges we find and a way to look up
      the host bridge from a pci_dev.
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      5a21d70d
    • B
      PCI: don't publish new root bus until it's fully initialized · a5390aa6
      Bjorn Helgaas 提交于
      When pci_create_root_bus() adds the new struct pci_bus to the global
      pci_root_buses list, the bus becomes visible to other parts of the
      kernel, so it should be fully initialized.
      
      This patch delays adding the bus to the pci_root_buses list until after
      all the struct pci_bus initialization is finished.
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      a5390aa6
    • Y
      PCI: fix memleak for pci dev removing during hotplug · f796841e
      Yinghai Lu 提交于
      unreferenced object 0xffff880276d17700 (size 64):
        comm "swapper/0", pid 1, jiffies 4294897182 (age 3976.028s)
        hex dump (first 32 bytes):
          00 00 00 00 00 00 00 00 18 f9 de 76 02 88 ff ff  ...........v....
          10 00 00 00 0e 00 00 00 0f 28 40 00 00 00 00 00  .........(@.....
        backtrace:
          [<ffffffff81c8aede>] kmemleak_alloc+0x26/0x43
          [<ffffffff811385f0>] __kmalloc+0x121/0x183
          [<ffffffff813cf821>] pci_add_cap_save_buffer+0x35/0x7c
          [<ffffffff813d12b7>] pci_allocate_cap_save_buffers+0x1d/0x65
          [<ffffffff813cdb52>] pci_device_add+0x92/0xf1
          [<ffffffff81c8afe6>] pci_scan_single_device+0x9f/0xa1
          [<ffffffff813cdbd2>] pci_scan_slot.part.20+0x21/0x106
          [<ffffffff813cdce2>] pci_scan_slot+0x2b/0x35
          [<ffffffff81c8dae4>] __pci_scan_child_bus+0x51/0x107
          [<ffffffff81c8d75b>] pci_scan_bridge+0x376/0x6ae
          [<ffffffff81c8db60>] __pci_scan_child_bus+0xcd/0x107
          [<ffffffff81c8dbab>] pci_scan_child_bus+0x11/0x2a
          [<ffffffff81cca58c>] pci_acpi_scan_root+0x18b/0x21c
          [<ffffffff81c916be>] acpi_pci_root_add+0x1e1/0x42a
          [<ffffffff81406210>] acpi_device_probe+0x50/0x190
          [<ffffffff814a0227>] really_probe+0x99/0x126
      
      Need to free saved_buffer for capabilities.
      Signed-off-by: NYinghai Lu <yinghai@kernel.org>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      f796841e
    • Y
      PCI: Fix device class print out · 2dd8ba92
      Yinghai Lu 提交于
      Found debug print of class is shifted.
      
      | pci 0000:f8:15.2: [8086:2b56] type 0 class 0x000600
      
      Code is trying to print class with 6 digits, but use shifted class with
      4 digits valid value as variable.
      
      Change to original dev->class directly.
      
      Also remove not needed calculating of local variable class, because it
      will be updated after pci_fixup_device(pci_fixup_early...)
      
      Also unify type print out when class and header is not matched.
      Signed-off-by: NYinghai Lu <yinghai@kernel.org>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      2dd8ba92
  2. 15 2月, 2012 3 次提交
  3. 11 2月, 2012 1 次提交
    • Y
      PCI: workaround hard-wired bus number V2 · 71f6bd4a
      Yinghai Lu 提交于
      Fixes PCI device detection on IBM xSeries IBM 3850 M2 / x3950 M2
      when using ACPI resources (_CRS).
      This is default, a manual workaround (without this patch)
      would be pci=nocrs boot param.
      
      V2: Add dev_warn if the workaround is hit. This should reveal
      how common such setups are (via google) and point to possible
      problems if things are still not working as expected.
      -> Suggested by Jan Beulich.
      
      Cc: stable@vger.kernel.org
      Tested-by: garyhade@us.ibm.com
      Signed-off-by: NYinghai Lu <yinghai.lu@oracle.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      71f6bd4a
  4. 07 1月, 2012 8 次提交
  5. 28 10月, 2011 2 次提交
  6. 05 10月, 2011 1 次提交
  7. 14 9月, 2011 1 次提交
  8. 10 9月, 2011 2 次提交
  9. 02 8月, 2011 2 次提交
    • J
      PCI: export pcie_bus_configure_settings symbol · debc3b77
      Jon Mason 提交于
      pcie_bus_configure_settings needs to be exported if the PCI hotplug
      driver is being compiled as a module.
      Reported-by: NStephen Rothwell <sfr@canb.auug.org.au>
      Signed-off-by: NJon Mason <mason@myri.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      debc3b77
    • J
      PCI: Set PCI-E Max Payload Size on fabric · b03e7495
      Jon Mason 提交于
      On a given PCI-E fabric, each device, bridge, and root port can have a
      different PCI-E maximum payload size.  There is a sizable performance
      boost for having the largest possible maximum payload size on each PCI-E
      device.  However, if improperly configured, fatal bus errors can occur.
      Thus, it is important to ensure that PCI-E payloads sends by a device
      are never larger than the MPS setting of all devices on the way to the
      destination.
      
      This can be achieved two ways:
      
      - A conservative approach is to use the smallest common denominator of
        the entire tree below a root complex for every device on that fabric.
      
      This means for example that having a 128 bytes MPS USB controller on one
      leg of a switch will dramatically reduce performances of a video card or
      10GE adapter on another leg of that same switch.
      
      It also means that any hierarchy supporting hotplug slots (including
      expresscard or thunderbolt I suppose, dbl check that) will have to be
      entirely clamped to 128 bytes since we cannot predict what will be
      plugged into those slots, and we cannot change the MPS on a "live"
      system.
      
      - A more optimal way is possible, if it falls within a couple of
        constraints:
      * The top-level host bridge will never generate packets larger than the
        smallest TLP (or if it can be controlled independently from its MPS at
        least)
      * The device will never generate packets larger than MPS (which can be
        configured via MRRS)
      * No support of direct PCI-E <-> PCI-E transfers between devices without
        some additional code to specifically deal with that case
      
      Then we can use an approach that basically ignores downstream requests
      and focuses exclusively on upstream requests. In that case, all we need
      to care about is that a device MPS is no larger than its parent MPS,
      which allows us to keep all switches/bridges to the max MPS supported by
      their parent and eventually the PHB.
      
      In this case, your USB controller would no longer "starve" your 10GE
      Ethernet and your hotplug slots won't affect your global MPS.
      Additionally, the hotplugged devices themselves can be configured to a
      larger MPS up to the value configured in the hotplug bridge.
      
      To choose between the two available options, two PCI kernel boot args
      have been added to the PCI calls.  "pcie_bus_safe" will provide the
      former behavior, while "pcie_bus_perf" will perform the latter behavior.
      By default, the latter behavior is used.
      
      NOTE: due to the location of the enablement, each arch will need to add
      calls to this function.  This patch only enables x86.
      
      This patch includes a number of changes recommended by Benjamin
      Herrenschmidt.
      
      Tested-by: Jordan_Hargrave@dell.com
      Signed-off-by: NJon Mason <mason@myri.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      b03e7495
  10. 23 7月, 2011 3 次提交
  11. 22 7月, 2011 1 次提交
  12. 08 6月, 2011 1 次提交
    • B
      pci/of: Match PCI devices to OF nodes dynamically · 98d9f30c
      Benjamin Herrenschmidt 提交于
      powerpc has two different ways of matching PCI devices to their
      corresponding OF node (if any) for historical reasons. The ppc64 one
      does a scan looking for matching bus/dev/fn, while the ppc32 one does a
      scan looking only for matching dev/fn on each level in order to be
      agnostic to busses being renumbered (which Linux does on some
      platforms).
      
      This removes both and instead moves the matching code to the PCI core
      itself. It's the most logical place to do it: when a pci_dev is created,
      we know the parent and thus can do a single level scan for the matching
      device_node (if any).
      
      The benefit is that all archs now get the matching for free. There's one
      hook the arch might want to provide to match a PHB bus to its device
      node. A default weak implementation is provided that looks for the
      parent device device node, but it's not entirely reliable on powerpc for
      various reasons so powerpc provides its own.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Acked-by: NMichal Simek <monstr@monstr.eu>
      Acked-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      98d9f30c
  13. 01 6月, 2011 1 次提交
    • D
      PCI: Fix warning in drivers/pci/probe.c on sparc64 · 5aceca9d
      David S. Miller 提交于
      IO_SPACE_LIMIT is currently used in two ways:
      
      1) As a way to mask I/O port values read out of PCI base address
         registers.  This value should be 64-bit.
      
      2) As a value which is the upper limit for all I/O "ports" in the
         system.
      
      On sparc64 we store the full 64-bit physical I/O address in the
      resources.  For this reason we define IO_SPACE_LIMIT at a 64-bit
      "all 1's".
      
      This is the right value to use for ioport_resource.end and for the
      check made in drivers/pcmcia/rsrc_nonstatic.c:adjust_io().
      
      But in driver/pci/probe.c:__pci_read_base() we mask this against
      a "u32" variable and thus get the following warning:
      
      drivers/pci/probe.c: In function ¡__pci_read_base¢:
      drivers/pci/probe.c:207: warning: large integer implicitly truncated to unsigned type
      
      Fix this by using an explicit "u32" cast.
      
      I considered changing sparc64 to define a 32-bit "all 1's" like
      most other systems do, but this wouldn't work because the checks
      in PCMCIA's rsrc_nonstatic.c would no longer be right since they
      are testing against fully formed 64-bit resources.  As described
      above, on sparc64 such resources will hold full 64-bit physical
      I/O addresses, not bus-centric 32-bit ones.
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      5aceca9d
  14. 22 5月, 2011 2 次提交
  15. 09 2月, 2011 1 次提交
    • J
      PCI: Avoid potential NULL pointer dereference in pci_scan_bridge · 7c867c88
      Jesper Juhl 提交于
      pci_add_new_bus() calls pci_alloc_child_bus() which calls pci_alloc_bus()
      that allocates memory dynamically with kzalloc(). The return value of
      kzalloc() is the pointer that's eventually returned from
      pci_add_new_bus(), so since kzalloc() can fail and return NULL so can
      pci_add_new_bus(). Thus we may end up dereferencing a NULL pointer in
      drivers/pci/probe.c::pci_scan_bridge(). Seems to me we should test for
      this and bail out if it happens rather than crashing.
      Also removed some trailing whitespace that bugged me while looking at
      this.
      Signed-off-by: NJesper Juhl <jj@chaosbits.net>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      7c867c88
  16. 18 10月, 2010 1 次提交
  17. 31 7月, 2010 1 次提交
  18. 20 5月, 2010 1 次提交
  19. 23 4月, 2010 1 次提交
  20. 25 3月, 2010 3 次提交