in some platforms, we found the max-read-request-size in Device Control
Register is set to 0 by (BIOS?) during bootup, this will cause the
performance(throughput) very bad.
Restore it to a min-value.
register definition of REG_DEVICE_CTRL is removed, using kernel API to
access it as it's a standard pcie register.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Tested-by: NLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

using fixed TXQ config for l2cb and l1c regardless dmar_block
to make tx-DMA more stable.
register REG_TXQ_CTRL is refined as well.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Tested-by: NLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

some fields of REG_DMA_CTRL(15C0) are wrong, replace with the newest one.
haredware uses fixed dma-write-block size, remove dmaw_block related code
in function atl1c_configure_dma.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Tested-by: NLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

remove code related to rxq 1/2/3 since multi-q not support.
refine REG_RXQ_CTRL definition as well.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Tested-by: NLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

TPD producer/consumer index is 16bit wide.
16bit read/write reduce the dependency of the 2 tpd rings (hi and lo)
rename reg(157C/1580) to keep name coninsistency.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Tested-by: NLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

l1c & later chips don't support DMA for SMB.
CMB is removed from hardware.
reg(15C8) is used to trig interrupt by tpd threshold.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Tested-by: NLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

VPD register is only used for L1(devid=PCI_DEVICE_ID_ATTANSIC_L1) to
access external NV-memory.
l1c & later chip doesn't use it any more.
PHY 0/1 registers occupy the last 2 slots of the dump table.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Tested-by: NLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

remove HDS register as it doesn't exist in hardware.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Tested-by: NLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

the multiple-RX-Q in hardware doesn't work,
all related register definition & code are removed.
Signed-off-by: Nxiong <xiong@qca.qualcomm.com>
Tested-by: NLiu David <dwliu@qca.qualcomm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Move the Atheros drivers into drivers/net/ethernet/atheros/ and
make the necessary Kconfig and Makefile changes.

CC: Jay Cliburn <jcliburn@gmail.com>
CC: Chris Snook <chris.snook@gmail.com>
CC: Jie Yang <jie.yang@atheros.com>
Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>

Either unused or duplicates from mii.h.
Signed-off-by: NFrancois Romieu <romieu@fr.zoreil.com>
Cc: Jay Cliburn <jcliburn@gmail.com>
Cc: Chris Snook <chris.snook@gmail.com>
Cc: Jie Yang <jie.yang@atheros.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Add AR8151 v2.0 Gigabit 1000 support
Change jumbo frame size to 6K
Update L0s/L1 rountine
        when link speed is 100M or 1G, set L1 link timer to 4 for l1d_2 and l2c_b2
        set L1 link timer to 7 for l2c_b, set L1 link timer to 0xF for others.
Update atl1c_suspend routine
	just refactory the function, add atl1c_phy_power_saving routine,
	when Wake On Lan enable, this func will be called to save power,
	it will reautoneg PHY to 10/100M speed depend on the link
	partners link capability.
Update atl1c_configure_des_ring
        do not use l2c_b default SRAM configuration.
Signed-off-by: NJie Yang <Jie.Yang@atheros.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

AR8151 is a Gigabit Ethernet device. AR8152 devices are
Fast Ethernet devices, there are two revisions, a 1.0
and a 2.0 revision.

This has been tested against these devices:

Driver	Model-name	vendor:device	Type
atl1c 	AR8131		1969:1063	Gigabit Ethernet
atl1c	AR8132		1969:1062	Fast Ethernet
atl1c	AR8151(v1.0)	1969:1073	Gigabit Ethernet
atl1c	AR8152(v1.1)	1969:2060	Fast Ethernet

This device has no hardware available yet so it goes untested,
but it should work:

atl1c	AR8152(v2.0)	1969:2062	Fast Ethernet
Signed-off-by: NLuis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Supporting AR8131, and AR8132.
Signed-off-by: NJie Yang <jie.yang@atheros.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>