1. 02 8月, 2021 1 次提交
  2. 24 7月, 2020 1 次提交
  3. 11 12月, 2019 2 次提交
  4. 08 10月, 2019 1 次提交
  5. 04 9月, 2019 1 次提交
  6. 05 6月, 2019 1 次提交
  7. 07 2月, 2019 1 次提交
  8. 06 12月, 2018 2 次提交
    • Y
      ASoC: use dma_ops of parent device for acp_audio_dma · 23aa128b
      Yu Zhao 提交于
      AMD platform device acp_audio_dma can only be created by parent PCI
      device driver (drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c). Pass struct
      device of the parent to snd_pcm_lib_preallocate_pages() so
      dma_alloc_coherent() can use correct dma_ops. Otherwise, it will
      use default dma_ops which is nommu_dma_ops on x86_64 even when
      IOMMU is enabled and set to non passthrough mode.
      
      Though platform device inherits some dma related fields during its
      creation in mfd_add_device(), we can't simply pass its struct device
      to snd_pcm_lib_preallocate_pages() because dma_ops is not among the
      inherited fields. Even it were, drivers/iommu/amd_iommu.c would
      ignore it because get_device_id() doesn't handle platform device.
      
      This change shouldn't give us any trouble even struct device of the
      parent becomes null or represents some non PCI device in the future,
      because get_dma_ops() correctly handles null struct device or uses
      the default dma_ops if struct device doesn't have it set.
      Signed-off-by: NYu Zhao <yuzhao@google.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      23aa128b
    • Y
      ASoC: use DMA addr rather than CPU pa for acp_audio_dma · d6d08273
      Yu Zhao 提交于
      We shouldn't assume CPU physical address we get from page_to_phys()
      is same as DMA address we get from dma_alloc_coherent(). On x86_64,
      we won't run into any problem with the assumption when dma_ops is
      nommu_dma_ops. However, DMA address is IOVA when IOMMU is enabled.
      And it's most likely different from CPU physical address when AMD
      IOMMU is not in passthrough mode.
      Signed-off-by: NYu Zhao <yuzhao@google.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      d6d08273
  9. 19 9月, 2018 1 次提交
    • A
      ASoC: AMD: Fix capture unstable in beginning for some runs · c50535ed
      Akshu Agrawal 提交于
      alsa_conformance_test -C hw:0,4 -p 1024 --debug
      would sometime show:
      TIME_DIFF(s)    HW_LEVEL       READ              RATE
      0.000095970         1024       1024    10670001.041992
      0.042609555         1024       2048       24032.168372
      0.021330364         1024       3072       48006.681930
      0.021339559         1024       4096       47985.996337
      The issue is that in dma pointer function we can have stale value
      of the register for current descriptor of channel.
      The register retains the number of the last descriptor that
      was transferred.
      
      Fix ensures that we report position, 0, till the one period worth of
      data is transferred.  After one period of data, in handler of period
      completion interrupt we update the config and correct value of descriptor
      starts reflecting.
      Signed-off-by: NAkshu Agrawal <akshu.agrawal@amd.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      c50535ed
  10. 11 9月, 2018 1 次提交
    • A
      ASoC: AMD: Fix simultaneous playback and capture on different channel · 8dcb0c90
      Akshu Agrawal 提交于
      If capture and playback are started on different channel (I2S/BT)
      there is a possibilty that channel information passed from machine driver
      is overwritten before the configuration is done in dma driver.
      Example:
      113.597588: cz_max_startup: ---playback sets BT channel
      113.597694: cz_dmic1_startup: ---capture sets I2S channel
      113.597979: acp_dma_hw_params: ---configures capture for I2S channel
      113.598114: acp_dma_hw_params: ---configures playback for I2S channel
      
      This is fixed by having 2 separate instance for playback and capture.
      Signed-off-by: NAkshu Agrawal <akshu.agrawal@amd.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      8dcb0c90
  11. 10 9月, 2018 1 次提交
  12. 07 8月, 2018 3 次提交
  13. 16 7月, 2018 2 次提交
  14. 03 7月, 2018 6 次提交
  15. 22 6月, 2018 1 次提交
  16. 18 6月, 2018 1 次提交
  17. 29 5月, 2018 1 次提交
  18. 21 5月, 2018 4 次提交
  19. 11 5月, 2018 3 次提交
  20. 02 5月, 2018 1 次提交
  21. 26 4月, 2018 1 次提交
  22. 18 4月, 2018 1 次提交
  23. 09 3月, 2018 2 次提交
  24. 19 2月, 2018 1 次提交