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  1. 27 3月, 2020 28 次提交
  3. 26 3月, 2020 9 次提交
  5. 25 3月, 2020 3 次提交
    • V
      net: phy: mscc: consolidate a common RGMII delay implementation · 2283a02b
      由 Vladimir Oltean 提交于 
      It looks like the VSC8584 PHY driver is rolling its own RGMII delay
configuration code, despite the fact that the logic is mostly the same.

In fact only the register layout and position for the RGMII controls has
changed. So we need to adapt and parameterize the PHY-dependent bit
fields when calling the new generic function.
Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
Tested-by: NAntoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      2283a02b
    • A
      net: axienet: Allow DMA to beyond 4GB · 5fff0151
      由 Andre Przywara 提交于 
      With all DMA address accesses wrapped, we can actually support 64-bit
DMA if this option was chosen at IP integration time.
If the IP has been configured for an address width greater than 32 bits,
we assume the full 64 bit DMA width is working. In practise this will be
limited by the actual system address bus width, which will ideally be the
same as the DMA IP address width.
If this is not the case, the actual width can still be configured using a
dma-ranges property in the parent of the MAC node.

This increases the DMA mask on those systems to let the kernel choose
buffers from memory at higher addresses.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      5fff0151
    • A
      net: axienet: Autodetect 64-bit DMA capability · f735c40e
      由 Andre Przywara 提交于 
      When newer revisions of the Axienet IP are configured for a 64-bit bus,
we *need* to write to the MSB part of the an address registers,
otherwise the IP won't recognise this as a DMA start condition.
This is even true when the actual DMA address comes from the lower 4 GB.

To autodetect this configuration, at probe time we write all 1's to such
an MSB register, and see if any bits stick. If this is configured for a
32-bit bus, those MSB registers are RES0, so reading back 0 indicates
that no MSB writes are necessary.
On the other hands reading anything other than 0 indicated the need to
write the MSB registers, so we set the respective flag.

The actual DMA mask stays at 32-bit for now. To help bisecting, a
separate patch will enable allocations from higher addresses.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      f735c40e