No code uses these, and the short define names are polluting the global
namespace where they collide with things like common irq files.  So just
punt the damned things.  If in the future we need HDMA support, we can
make a standalone header for these things.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Hook up name_to_handle_at, open_by_handle_at, and clock_adjtime.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

This patch fixes the Blackfin irqflags to make them I-pipe aware anew,
after the introduction of the hard_local_irq_*() API.
Signed-off-by: NPhilippe Gerum <rpm@xenomai.org>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

This patch makes sure to sync the pipeline for the root stage only
from the outer interrupt level, when resuming kernel code after an
interrupt.

This fixes a bug causing EVT15 to be spuriously popped off upon nested
interrupts, which in turn would cause the preempted kernel code to
resume without supervisor privileges.
Signed-off-by: NPhilippe Gerum <rpm@xenomai.org>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

This patch introduces Blackfin-specific bits to support the current
tip of the interrupt pipeline development, mainly:

- 2/3-level interrupt maps (sparse IRQs)
- generic virq handling
- sysinfo v2 format for ipipe_get_sysinfo()
Signed-off-by: NPhilippe Gerum <rpm@xenomai.org>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

No functional changes here.
Signed-off-by: NMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

All chips converted.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Fixup the open coded access to irq_desc and use the proper wrappers.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Take advantage of more Blackfin-specific insns, and only initialize
registers required by the ABI.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

In order to safely work around anomaly 05000491, we have to execute IFLUSH
from L1 instruction sram.  The trouble with multi-core systems is that all
L1 sram is visible only to the active core.  So we can't just place the
functions into L1 and call it directly.  We need to setup a jump table and
place the entry point in external memory.  This will call the right func
based on the active core.

In the process, convert from the manual relocation of a small bit of code
into Core B's L1 to the more general framework we already have in place
for loading arbitrary pieces of code into L1.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Re-use some of the existing cpu hotplugging code in the process.
Signed-off-by: NGraf Yang <graf.yang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

We need to place icache flush funcs into L1 inst sram to work around a
hardware anomaly.  But this currently breaks SMP support as the L1 inst
sram is per-core and cannot be called directly.  So in preparation for
making that work, split the two options.

Further, split out the SMP depend so that we can allow some for SMP.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The smp_processor_id() API requires that preempt be disabled when calling
it, so make sure it is when we go to send messages to other processors.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Defer bfin_setup_caches(cpu) to avoid unexpected faults due to the cpu
state not yet being fully initialized.
Signed-off-by: Nsteven miao <realmz6@gmail.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Common code checks the alignment of some of the variables and calls BUG()
if they aren't page aligned.
Signed-off-by: Nsteven miao <realmz6@gmail.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

We use these insns when testing, so enable them by default for all
of our development boards.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Common code no longer defines this, so stop using it.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The board doesn't actually have a pin hooked up to do card detection,
so punt the code for it.
Signed-off-by: NAndreas Schallenberg <Andreas.Schallenberg@3alitydigital.de>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NAaron Wu <aaronwu06@gmail.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The BF54x lacks dedicated DMA channels for the UART peripherals and need
to be muxed between others.  So add a kconfig option so people can select
which channels the UARTs will use so they can pick between SPORTs and the
less commonly used EPPI/PIXC peripherals.
Signed-off-by: Nsteven miao <realmz6@gmail.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Since coreb_trampoline_start() calls coreb_start(), they need to be in
the same section.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

This change supports building the kernel with newer binutils where
a shift of greater than the word size is no longer interpreted
silently as modulo the word size, but instead generates a warning.
Signed-off-by: NChris Metcalf <cmetcalf@tilera.com>

Commit 6440e5967bc broke old userspaces that do not set tss address
before entering vcpu. Unbreak it by setting tss address to a safe
value on the first vcpu entry. New userspaces should set tss address,
so print warning in case it doesn't.
Signed-off-by: NGleb Natapov <gleb@redhat.com>
Signed-off-by: NMarcelo Tosatti <mtosatti@redhat.com>

This patch does:
- call vcpu->arch.mmu.update_pte directly
- use gfn_to_pfn_atomic in update_pte path

The suggestion is from Avi.
Signed-off-by: NXiao Guangrong <xiaoguangrong@cn.fujitsu.com>
Signed-off-by: NAvi Kivity <avi@redhat.com>

Cleanup the code of pte_prefetch_gfn_to_memslot and mapping_level_dirty_bitmap
Signed-off-by: NXiao Guangrong <xiaoguangrong@cn.fujitsu.com>
Signed-off-by: NAvi Kivity <avi@redhat.com>

fix:
[ 3494.671786] stack backtrace:
[ 3494.671789] Pid: 10527, comm: qemu-system-x86 Not tainted 2.6.38-rc6+ #23
[ 3494.671790] Call Trace:
[ 3494.671796]  [] ? lockdep_rcu_dereference+0x9d/0xa5
[ 3494.671826]  [] ? kvm_memslots+0x6b/0x73 [kvm]
[ 3494.671834]  [] ? gfn_to_memslot+0x16/0x4f [kvm]
[ 3494.671843]  [] ? gfn_to_hva+0x16/0x27 [kvm]
[ 3494.671851]  [] ? kvm_write_guest_page+0x31/0x83 [kvm]
[ 3494.671861]  [] ? kvm_clear_guest_page+0x1a/0x1c [kvm]
[ 3494.671867]  [] ? vmx_set_tss_addr+0x83/0x122 [kvm_intel]

and:
[ 8328.789599] stack backtrace:
[ 8328.789601] Pid: 18736, comm: qemu-system-x86 Not tainted 2.6.38-rc6+ #23
[ 8328.789603] Call Trace:
[ 8328.789609]  [] ? lockdep_rcu_dereference+0x9d/0xa5
[ 8328.789621]  [] ? kvm_memslots+0x6b/0x73 [kvm]
[ 8328.789628]  [] ? gfn_to_memslot+0x16/0x4f [kvm]
[ 8328.789635]  [] ? gfn_to_hva+0x16/0x27 [kvm]
[ 8328.789643]  [] ? kvm_write_guest_page+0x31/0x83 [kvm]
[ 8328.789699]  [] ? kvm_clear_guest_page+0x1a/0x1c [kvm]
[ 8328.789713]  [] ? vmx_create_vcpu+0x316/0x3c8 [kvm_intel]
Signed-off-by: NXiao Guangrong <xiaoguangrong@cn.fujitsu.com>
Signed-off-by: NAvi Kivity <avi@redhat.com>

commit 387b9f97750444728962b236987fbe8ee8cc4f8c moved kvm_request_guest_time_update(vcpu),
breaking 32bit SMP guests using kvm-clock. Fix this by moving (new) clock update function
to proper place.
Signed-off-by: NNikola Ciprich <nikola.ciprich@linuxbox.cz>
Acked-by: NZachary Amsden <zamsden@redhat.com>
Signed-off-by: NAvi Kivity <avi@redhat.com>

Currently if io port + len crosses 8bit boundary in io permission bitmap the
check may allow IO that otherwise should not be allowed. The patch fixes that.
Signed-off-by: NGleb Natapov <gleb@redhat.com>
Signed-off-by: NAvi Kivity <avi@redhat.com>

Current implementation truncates upper 32bit of TR base address during IO
permission bitmap check. The patch fixes this.
Reported-and-tested-by: NFrancis Moreau <francis.moro@gmail.com>
Signed-off-by: NGleb Natapov <gleb@redhat.com>
Signed-off-by: NAvi Kivity <avi@redhat.com>

With CONFIG_CC_STACKPROTECTOR, we need a valid %gs at all times, so disable
lazy reload and do an eager reload immediately after the vmexit.
Reported-by: NIVAN ANGELOV <ivangotoy@gmail.com>
Acked-By: NJoerg Roedel <joerg.roedel@amd.com>
Signed-off-by: NAvi Kivity <avi@redhat.com>