1. 23 9月, 2016 1 次提交
    • K
      PCI: pciehp: Allow exclusive userspace control of indicators · 576243b3
      Keith Busch 提交于
      PCIe hotplug supports optional Attention and Power Indicators, which are
      used internally by pciehp.  Users can't control the Power Indicator, but
      they can control the Attention Indicator by writing to a sysfs "attention"
      file.
      
      The Slot Control register has two bits for each indicator, and the PCIe
      spec defines the encodings for each as (Reserved/On/Blinking/Off).  For
      sysfs "attention" writes, pciehp_set_attention_status() maps into these
      encodings, so the only useful write values are 0 (Off), 1 (On), and 2
      (Blinking).
      
      However, some platforms use all four bits for platform-specific indicators,
      and they need to allow direct user control of them while preventing pciehp
      from using them at all.
      
      Add a "hotplug_user_indicators" flag to the pci_dev structure.  When set,
      pciehp does not use either the Attention Indicator or the Power Indicator,
      and the low four bits (values 0x0 - 0xf) of sysfs "attention" write values
      are written directly to the Attention Indicator Control and Power Indicator
      Control fields.
      
      [bhelgaas: changelog, rename flag and accessors to s/attention/indicator/]
      Signed-off-by: NKeith Busch <keith.busch@intel.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      576243b3
  2. 15 9月, 2016 7 次提交
  3. 13 9月, 2016 1 次提交
  4. 23 8月, 2016 1 次提交
  5. 05 8月, 2016 1 次提交
  6. 04 8月, 2016 1 次提交
  7. 20 7月, 2016 1 次提交
    • T
      PCI: rpaphp: Fix slot registration for multiple slots under a PHB · e2413a7d
      Tyrel Datwyler 提交于
      The underlying slot hotplug registration code assumed multiple slots, but
      the actual implementation is broken for multiple slots.
      
      This went unnoticed for years do to the fact that PowerVM seems to only
      ever provide a single hotplug slot per PHB.
      
      Under qemu/kvm the hotplug slot model aligns more with x86 where
      multiple slots are presented under a single PHB. As seen in the
      following each additional slot after the first fails to register due to
      each slot always being compared against the first child node of the PHB
      in the device tree.
      
        rpaphp: RPA HOT Plug PCI Controller Driver version: 0.1
        rpaphp: Slot [Slot 0] registered
        rpaphp: pci_hp_register failed with error -16
        rpaphp: pci_hp_register failed with error -16
        rpaphp: pci_hp_register failed with error -16
        rpaphp: pci_hp_register failed with error -16
      
      The registration logic is fixed so that each slot is compared
      against the existing child devices of the PHB in the device tree to
      determine present slots vs empty slots.
      
        rpaphp: RPA HOT Plug PCI Controller Driver version: 0.1
        rpaphp: Slot [C0] registered
        rpaphp: Slot [C1] registered
        rpaphp: Slot [C2] registered
        rpaphp: Slot [C3] registered
        rpaphp: Slot [C4] registered
      Signed-off-by: NTyrel Datwyler <tyreld@linux.vnet.ibm.com>
      Reviewed-by: NNathan Fontenot <nfont@linux.vnet.ibm.com>
      [mpe: Massage changelog]
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      e2413a7d
  8. 14 7月, 2016 2 次提交
  9. 21 6月, 2016 2 次提交
    • G
      PCI/hotplug: PowerPC PowerNV PCI hotplug driver · 66725152
      Gavin Shan 提交于
      This adds standalone driver to support PCI hotplug for PowerPC PowerNV
      platform that runs on top of skiboot firmware. The firmware identifies
      hotpluggable slots and marked their device tree node with proper
      "ibm,slot-pluggable" and "ibm,reset-by-firmware". The driver scans
      device tree nodes to create/register PCI hotplug slot accordingly.
      
      The PCI slots are organized in fashion of tree, which means one
      PCI slot might have parent PCI slot and parent PCI slot possibly
      contains multiple child PCI slots. At the plugging time, the parent
      PCI slot is populated before its children. The child PCI slots are
      removed before their parent PCI slot can be removed from the system.
      
      If the skiboot firmware doesn't support slot status retrieval, the PCI
      slot device node shouldn't have property "ibm,reset-by-firmware". In
      that case, none of valid PCI slots will be detected from device tree.
      The skiboot firmware doesn't export the capability to access attention
      LEDs yet and it's something for TBD.
      Signed-off-by: NGavin Shan <gwshan@linux.vnet.ibm.com>
      Acked-by: NBjorn Helgaas <bhelgaas@google.com>
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      66725152
    • L
      PCI: pciehp: Ignore interrupts during D3cold · ed91de7e
      Lukas Wunner 提交于
      If a hotplug port is suspended to D3cold, its slot status register cannot
      be read.  If that hotplug port happens to share its IRQ with other devices,
      whenever an interrupt occurs for one of these devices, pciehp logs a
      "no response from device" message and tries to read the PCI_EXP_SLTSTA
      register, even though we know that will fail.
      
      Ignore interrupts while we're in D3cold.
      
      [bhelgaas: changelog]
      Signed-off-by: NLukas Wunner <lukas@wunner.de>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      ed91de7e
  10. 14 6月, 2016 1 次提交
  11. 11 5月, 2016 2 次提交
  12. 15 4月, 2016 1 次提交
  13. 23 2月, 2016 1 次提交
  14. 24 1月, 2016 1 次提交
  15. 11 1月, 2016 2 次提交
  16. 09 1月, 2016 4 次提交
  17. 11 12月, 2015 1 次提交
    • B
      PCI: Check for PCI_HEADER_TYPE_BRIDGE equality, not bitmask · 93de6901
      Bjorn Helgaas 提交于
      Bit 7 of the "Header Type" register indicates a multi-function device when
      set.  Bits 0-6 contain encoded values, where 0x1 indicates a PCI-PCI
      bridge.  It is incorrect to test this as though it were a mask.
      
      For example, while the PCI 3.0 spec only defines values 0x0, 0x1, and 0x2,
      it's conceivable that a future spec could define 0x3 to mean something
      else; then tests for "(hdr_type & 0x7f) & PCI_HEADER_TYPE_BRIDGE" would
      incorrectly succeed for this new 0x3 header type.
      
      Test bits 0-6 of the Header Type for equality with PCI_HEADER_TYPE_BRIDGE.
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      93de6901
  18. 26 11月, 2015 1 次提交
  19. 22 10月, 2015 1 次提交
    • G
      PCI: pciehp: Queue power work requests in dedicated function · bee67756
      Guenter Roeck 提交于
      Up to now, work items to be queued to be handled by pciehp_power_thread()
      are allocated using kmalloc() in three different locations.  If not needed,
      kfree() is called to free the allocated data.
      
      Introduce a separate function to allocate the work item and queue it, and
      call it only if needed.  This reduces code duplication and avoids having to
      free memory if the work item does not need to get executed.
      
      [bhelgaas: tweak "no memory" message, make pciehp_queue_power_work() static]
      Signed-off-by: NGuenter Roeck <linux@roeck-us.net>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      bee67756
  20. 11 8月, 2015 3 次提交
    • B
      PCI: pciehp: Remove ignored MRL sensor interrupt events · 2db0f71f
      Bjorn Helgaas 提交于
      We queued interrupt events for the MRL being opened or closed, but the code
      in interrupt_event_handler() that handles these events ignored them.
      
      Stop enabling MRL interrupts and remove the ignored events.
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      2db0f71f
    • B
      PCI: pciehp: Remove unused interrupt events · 58fa2405
      Bjorn Helgaas 提交于
      The list of interrupt events (INT_BUTTON_IGNORE, INT_PRESENCE_ON, etc.) was
      copied from other hotplug drivers, but pciehp doesn't use them all.
      
      Remove the interrupt events that aren't used by pciehp.
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      58fa2405
    • J
      PCI: pciehp: Handle invalid data when reading from non-existent devices · 1469d17d
      Jarod Wilson 提交于
      It's platform-dependent, but an MMIO read to a non-existent PCI device
      generally returns data with all bits set.  This happens when the host
      bridge or Root Complex times out waiting for a response from the device and
      fabricates return data to complete the CPU's read.
      
      One example, reported in the bugzilla below, involved this hierarchy:
      
        pci 0000:00:1c.0: PCI bridge to [bus 02-3a] Root Port
        pci 0000:02:00.0: PCI bridge to [bus 03-0a] Upstream Port
        pci 0000:03:03.0: PCI bridge to [bus 05-07] Downstream Port
        pci 0000:05:00.0: PCI bridge to [bus 06-07] Thunderbolt Upstream Port
        pci 0000:06:00.0: PCI bridge to [bus 07]    Thunderbolt Downstream Port
        pci 0000:07:00.0: BCM57762 NIC
      
      Unplugging the Thunderbolt switch and the NIC below it resulted in this:
      
        pciehp 0000:03:03.0: Surprise Removal
        tg3 0000:07:00.0: tg3_abort_hw timed out, TX_MODE_ENABLE will not clear MAC_TX_MODE=ffffffff
        pciehp 0000:06:00.0: unloading service driver pciehp
        pciehp 0000:06:00.0: pcie_isr: intr_loc 11f
        pciehp 0000:06:00.0: Switch interrupt received
        pciehp 0000:06:00.0: Latch open on Slot
        pciehp 0000:06:00.0: Attention button interrupt received
        pciehp 0000:06:00.0: Button pressed on Slot
        pciehp 0000:06:00.0: Presence/Notify input change
        pciehp 0000:06:00.0: Card present on Slot
        pciehp 0000:06:00.0: Power fault interrupt received
        pciehp 0000:06:00.0: Data Link Layer State change
        pciehp 0000:06:00.0: Link Up event
      
      The pciehp driver correctly noticed that the Thunderbolt switch (05:00.0
      and 06:00.0) and NIC (07:00.0) had been removed, and it called their driver
      remove methods.
      
      Since the NIC was already gone, tg3 received 0xffffffff when it tried to
      read from the device.  The resulting timeout is a tg3 issue and not of
      interest here.
      
      Similarly, since the 06:00.0 Thunderbolt switch was already gone,
      pcie_isr() received 0xffff when it tried to read PCI_EXP_SLTSTA, and pciehp
      thought that was valid status showing that many events had happened: the
      latch had been opened, the attention button had been pressed, a card was
      now present, and the link was now up.  These are all wrong, of course, but
      pciehp went on to try to power up and enumerate devices below the
      non-existent bridge:
      
        pciehp 0000:06:00.0: PCI slot - powering on due to button press
        pciehp 0000:06:00.0: Surprise Insertion
        pci 0000:07:00.0 id reading try 50 times with interval 20 ms to get ffffffff
      
      [bhelgaas: changelog, also check in pcie_poll_cmd() & pcie_do_write_cmd()]
      Link: https://bugzilla.kernel.org/show_bug.cgi?id=99841Suggested-by: NBjorn Helgaas <bhelgaas@google.com>
      Signed-off-by: NJarod Wilson <jarod@redhat.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      1469d17d
  21. 16 7月, 2015 2 次提交
  22. 19 6月, 2015 3 次提交