Add initial pinctrl driver to support pin configuration with
pinctrl framework for SM8150
Signed-off-by: NPrasad Sodagudi <psodagud@codeaurora.org>
Signed-off-by: NIsaac J. Manjarres <isaacm@codeaurora.org>
[vkoul: modify to use upstream tile support
	use upstream code style
	order the functions and squash functions]
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20190702105045.27646-4-vkoul@kernel.orgReviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add the binding for the TLMM pinctrl block found in the SM8150 platform.
Signed-off-by: NPrasad Sodagudi <psodagud@codeaurora.org>
Signed-off-by: NIsaac J. Manjarres <isaacm@codeaurora.org>
[vkoul: add missing nodes of gpio range and reserved
	rewrote function names and order them]
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20190702105045.27646-3-vkoul@kernel.orgReviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The bindings for msm8998-pinctrl was missing gpio-ranges and
gpio-reserved-ranges, so document them as well
Signed-off-by: NVinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20190702105045.27646-2-vkoul@kernel.orgReviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The ASPEED pinctrl driver implementations make heavy use of macros to
minimise tedium of implementation and maximise the chance that the
compiler will catch errors in defining signal and pin configurations.
While the goal of minimising errors is achieved, it is at the cost of
the complexity of the macros.

Document examples of the expanded form of pin declarations to
demonstrate the operation of the macros.

Cc: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: NAndrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190628023838.15426-9-andrew@aj.id.auSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

ASPEED have completely rearranged the System Control Unit register
layout with the AST2600. The existing code took advantage of the fact
that the AST2400 and AST2500 had layouts that were similar enough to
have little impact on the pinmux infrastructure (though there is a wart
with read-modify-write vs write-1-clear semantics of the hardware
strapping registers between the two).

Given that any similarity has been thrown out with the AST2600, separate
out the function applying an expression state to be driver-specific.
With it, extract out the pinmux macro jungle to its own header and
implementation so the pieces can be composed without dependency cycles.

Cc: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: NAndrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190628023838.15426-8-andrew@aj.id.auSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

Writes of 1 to SCU7C clear set bits in SCU70, the hardware strapping
register. The information was correct if you squinted while reading, but
hopefully switching the order of the registers as listed conveys it
better.

Cc: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: NAndrew Jeffery <andrew@aj.id.au>
Acked-by: NJoel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20190628023838.15426-7-andrew@aj.id.auSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

We have handled the GFX register case for quite some time now.

Cc: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: NAndrew Jeffery <andrew@aj.id.au>
Acked-by: NJoel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20190628023838.15426-6-andrew@aj.id.auSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add myself as maintainer to avoid burdening others with the madness.

Cc: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: NAndrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190628023838.15426-5-andrew@aj.id.auSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

Convert ASPEED pinctrl bindings to DT schema format using json-schema.

Cc: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: NAndrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190628023838.15426-4-andrew@aj.id.auSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

Convert ASPEED pinctrl bindings to DT schema format using json-schema

Cc: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: NAndrew Jeffery <andrew@aj.id.au>
Link: https://lore.kernel.org/r/20190628023838.15426-3-andrew@aj.id.auReviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Have one for each of the AST2400 and AST2500. The only thing that was
common was the fact that both support ASPEED BMC SoCs.

Cc: Johnny Huang <johnny_huang@aspeedtech.com>
Signed-off-by: NAndrew Jeffery <andrew@aj.id.au>
Acked-by: NJoel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20190628023838.15426-2-andrew@aj.id.auSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

Introduce the irq_enable callback which will be same as irq_unmask
except that it will also clear the status bit before unmask.

This will help in clearing any erroneous interrupts that would
have got latched when the interrupt is not in use.

There may be devices like UART which can use the same gpio line
for data rx as well as a wakeup gpio when in suspend. The data that
was flowing on the line may latch the interrupt and when we enable
the interrupt before going to suspend, this would trigger the
unexpected interrupt. This change helps clearing the interrupt
so that these unexpected interrupts gets cleared.
Signed-off-by: NSrinivas Ramana <sramana@codeaurora.org>
Signed-off-by: NNeeraj Upadhyay <neeraju@codeaurora.org>
Link: https://lore.kernel.org/r/1561472086-23360-1-git-send-email-neeraju@codeaurora.orgSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

GPL-2.0-only is the preferred way of expressing v2 of the GPL, so switch
to that. Remove some redundant copyright notices and correct some
instances where the wrong comment type has been used in header files.
Signed-off-by: NCharles Keepax <ckeepax@opensource.cirrus.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Clang warns when CONFIG_ACPI is unset:

 drivers/pinctrl/qcom/pinctrl-sdm845.c:1320:5: warning: 'CONFIG_ACPI' is
 not defined, evaluates to 0 [-Wundef]
 #if CONFIG_ACPI
     ^
 1 warning generated.

Use ifdef instead of if to resolve this.

Fixes: a229105d ("pinctrl: qcom: sdm845: Provide ACPI support")
Link: https://github.com/ClangBuiltLinux/linux/issues/569Signed-off-by: NNathan Chancellor <natechancellor@gmail.com>
Reviewed-by: NNick Desaulniers <ndesaulniers@google.com>
Acked-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Some pin groups have park bits for multiple pins in one register.
Support this by turning the parked bit field into a parked bitmask
field. If no parked bits are supported, the bitmask can be 0.

Update the pingroup table on Tegra210, which is the only generation
where this is supported, with the parked bitmask.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Tested-by: NDmitry Osipenko <digetx@gmail.com>
Reviewed-by: NDmitry Osipenko <digetx@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Rather than reuse the nvidia,tegra30-gpio compatible string
to find the GPIO controller on Tegra30, Tegra114, Tegra124 and
Tegra210, use the most specific compatible string for each
SoC generation for consistency.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Reviewed-by: NDmitry Osipenko <digetx@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The 98DX1135 is a switch chip with an integrated CPU. This is similar to
the 98DX4122 except the MPP assignments differ.
Signed-off-by: NChris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The 98DX1135 is similar to the 98DX4122 except the MPP options differ.
Signed-off-by: NChris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

What is the point in surrounding the whole of declarations with
ifdef like this?

  #ifdef CONFIG_FOO
  int foo(void);
  #endif

If CONFIG_FOO is not defined, all callers of foo() will fail
with implicit declaration errors since the top Makefile adds
-Werror-implicit-function-declaration to KBUILD_CFLAGS.

This breaks the build earlier when you are doing something wrong.
That's it.

Anyway, it will fail to link since the definition of foo() is not
compiled.

In summary, these ifdef are unneeded.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add the pinctrl driver support for i.MX8MN.
Signed-off-by: NAnson Huang <Anson.Huang@nxp.com>
Acked-by: NDong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add binding doc for i.MX8MN pinctrl driver.
Signed-off-by: NAnson Huang <Anson.Huang@nxp.com>
Acked-by: NDong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

OK so some automatic scripts were fixing the SPDX tags in
the mainline branch while we were patching other stuff,
and yeah it is more correct to have "GPL-2.0-only" rather
than "GPL-2.0" so let's conform to what is already upstream
so we don't end up getting the wrong license on the merged
result later.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This header uses 'bool', but it does not include any header by itself.

So, it could cause unknown type name error, depending on the header
include order, although probably <linux/types.h> has been included by
someone else.

Include <linux/types.h> to make it self-contained.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This fixes the warnings:

* include/linux/gpio.h:254:11: warning: 'struct pinctrl_dev' declared
  inside parameter list will not be visible outside of this definition
  or declaration
* include/linux/gpio/driver.h:602:11: warning: 'struct pinctrl_dev'
  declared inside parameter list will not be visible outside of this
  definition or declaration

Fixes: 78b99577 ("pinctrl: remove unused pin_is_valid()")
Reported-by: Nkbuild test robot <lkp@intel.com>
Signed-off-by: NEnrico Weigelt <info@metux.net>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The Allwinner V3 SoC, despite come with the same die with V3s, has more
GPIO pins than V3s, and a different compatible string for pinctrl is
needed.

Add the compatible string for V3 pinctrl.
Signed-off-by: NIcenowy Zheng <icenowy@aosc.io>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The pinctrl driver of V3s is already available and used in the kernel,
but the compatible string of it is forgotten to be added.

Add the missing compatible string.
Signed-off-by: NIcenowy Zheng <icenowy@aosc.io>
Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch provides basic support for booting with ACPI instead
of the currently supported Device Tree.  When doing so there are a
couple of differences which we need to taken into consideration.

Firstly, the SDM850 ACPI tables omit information pertaining to the
4 reserved GPIOs on the platform.  If Linux attempts to touch/
initialise any of these lines, the firmware will restart the
platform.

Secondly, when booting with ACPI, it is expected that the firmware
will set-up things like; Regulators, Clocks, Pin Functions, etc in
their ideal configuration.  Thus, the possible Pin Functions
available to this platform are not advertised when providing the
higher GPIOD/Pinctrl APIs with pin information.
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

When booting MSM based platforms with Device Tree or some ACPI
implementations, it is possible to provide a list of reserved pins
via the 'gpio-reserved-ranges' and 'gpios' properties respectively.
However some ACPI tables are not populated with this information,
thus it has to come from a knowledgable device driver instead.

Here we provide the MSM common driver with additional support to
parse this informtion and correctly populate the widely used
'valid_mask'.
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This function was used by pin_request() to pointlessly double-check
the pin validity, and it was the only user ever.

Since commit d2f6a1c6 ("pinctrl: remove double pin validity
check."), no one has ever used it.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The iterator is initialized in list_for_each_entry().
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Merge tag 'sh-pfc-for-v5.3-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v5.3

  - Add more checks for pinctrl table validation,
  - Add TPU (Timer Pulse Unit / PWM) pin groups on R-Car H3, M3-W, and
    M3-N,
  - Rework description of pins without GPIO functionality,
  - Small fixes and cleanups.

Some files were missing the appropriate SPDX tags so
fixed it up.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Update the code to use a flexible array member instead of a pointer in
structure tb10x_pinctrl and use the struct_size() helper:

struct tb10x_pinctrl {
        ...
	struct tb10x_of_pinfunc pinfuncs[];
};

Also, make use of the struct_size() helper instead of an open-coded
version in order to avoid any potential type mistakes.

So, replace the following form:

sizeof(struct tb10x_pinctrl) + of_get_child_count(of_node) * sizeof(struct tb10x_of_pinfunc)

with:

struct_size(state, pinfuncs, of_get_child_count(of_node))

This code was detected with the help of Coccinelle.
Reviewed-by: NKees Cook <keescook@chromium.org>
Signed-off-by: NGustavo A. R. Silva <gustavo@embeddedor.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add SGPM pinmux to ast2500-pinctrl function and group, to prepare for
supporting SGPIO in AST2500 SoC.
Signed-off-by: NHongwei Zhang <hongweiz@ami.com>
Reviewed-by: NAndrew Jeffery <andrew@aj.id.au>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The ufs_reset pin is expected to be wired to the reset pin of the
primary UFS memory but is pretty much just a general purpose output pinr

Reorder the pins and expose it as gpio 150, so that the UFS driver can
toggle it.
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add drive strength support for Bitmain BM1880 SoC.
Signed-off-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Document drive strength settings for Bitmain BM1880 SoC.
Signed-off-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>