- 11 1月, 2017 7 次提交
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由 Icenowy Zheng 提交于
V3s SoC features only a pin controller (for the lack of CPUs part). Add a driver for this controller. Signed-off-by: NIcenowy Zheng <icenowy@aosc.xyz> Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Dan Carpenter 提交于
We accidentally deleted two tabs from the first line, but even with that fixed the conditions were not really kernel style. Put the && at the end of the line so we can align the condition clauses. Also add spaces around the "+" operator. Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Fabio Estevam 提交于
Fix a typo in "Peripherals". Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Bjorn Andersson 提交于
Upon failing kzalloc() will print an error message in the log, so there's no need for additional printouts. Also standardizes the "!ptr" vs "ptr == NULL" while I'm touching those lines. Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 David Lechner 提交于
This adds the pintrol-da850-pupd driver to the module device table so that udev will automatically bind the driver to the device. Signed-off-by: NDavid Lechner <david@lechnology.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Andy Shevchenko 提交于
This simplifies error handling and allows us to drop error path handlers completely. Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Mika Westerberg 提交于
This simplifies error handling and allows us to drop intel_pinctrl_remove() completely. Signed-off-by: NMika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: NAndy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 10 1月, 2017 2 次提交
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由 Nishanth Menon 提交于
SoC family such as DRA7 family of processors have, in addition to the regular muxing of pins (as done by pinctrl-single), a separate hardware module called IODelay which is also expected to be configured. The "IODelay" module has it's own register space that is independent of the control module and the padconf register area. With recent changes to the pinctrl framework, we can now support this hardware with a reasonably minimal driver by using #pinctrl-cells, GENERIC_PINCTRL_GROUPS and GENERIC_PINMUX_FUNCTIONS. It is advocated strongly in TI's official documentation considering the existing design of the DRA7 family of processors during mux or IODelay reconfiguration, there is a potential for a significant glitch which may cause functional impairment to certain hardware. It is hence recommended to do as little of muxing as absolutely necessary without I/O isolation (which can only be done in initial stages of bootloader). NOTE: with the system wide I/O isolation scheme present in DRA7 SoC family, it is not reasonable to do stop all I/O operations for every such pad configuration scheme. So, we will let it glitch when used in this mode. Even with the above limitation, certain functionality such as MMC has mandatory need for IODelay reconfiguration requirements, depending on speed of transfer. In these cases, with careful examination of usecase involved, the expected glitch can be controlled such that it does not impact functionality. In short, IODelay module support as a padconf driver being introduced here is not expected to do SoC wide I/O Isolation and is meant for a limited subset of IODelay configuration requirements that need to be dynamic and whose glitchy behavior will not cause functionality failure for that interface. IMPORTANT NOTE: we take the approach of keeping LOCK_BITs cleared to 0x0 at all times, even when configuring Manual IO Timing Modes. This is done by eliminating the LOCK_BIT=1 setting from Step of the Manual IO timing Mode configuration procedure. This option leaves the CFG_* registers unprotected from unintended writes to the CTRL_CORE_PAD_* registers while Manual IO Timing Modes are configured. This approach is taken to allow for a generic driver to exist in kernel world that has to be used carefully in required usecases. Signed-off-by: NNishanth Menon <nm@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com> [tony@atomide.com: updated to use generic pinctrl functions, added binding documentation, updated comments] Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Tony Lindgren 提交于
If the pin controller driver is using devm_kzalloc, there may not be anything to do for dt_free_map. Let's make it optional to avoid unncessary boilerplate code. Signed-off-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 09 1月, 2017 3 次提交
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由 Maxime Ripard 提交于
Now that we have a common pinctrl driver for all the sun5i SoCs, we can remove the old, separate drivers. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Maxime Ripard 提交于
The sun5i SoCs (A10s, A13, GR8) are all based on the same die fit in different packages. Hence, the pins and functions available are just the based on the same set, each SoC having a different subset. Introduce a common pinctrl driver that supports multiple variants to allow to put as much as we can in common. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Maxime Ripard 提交于
Some SoCs are either supposed to be pin compatible (A10 and A20 for example), or are just repackaged versions of the same die (A10s, A13, GR8). In those case, having a full blown pinctrl driver just introduces duplication in both data size and maintainance effort. Add a variant option to both pins and functions to be able to limit the pins and functions described only to a subset of the SoC we support with a given driver. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 06 1月, 2017 1 次提交
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由 Jon Hunter 提交于
Commit df61b366af26 ('pinctrl: core: Use delayed work for hogs') deferred part of the registration for pinctrl devices if the pinctrl device has hogs. This introduced a window where if the pinctrl device with hogs was sucessfully registered, but then unregistered again (which could be caused by parent device being probe deferred) before the delayed work has chanced to run, then this will cause a kernel panic to occur because: 1. The 'pctldev->p' has not yet been initialised and when unregistering the pinctrl device we only check to see if it is an error value, but now it could also be NULL. 2. The pinctrl device may not have been added to the 'pinctrldev_list' list and we don't check to see if it was added before removing. Fix up the above by checking to see if the 'pctldev->p' pointer is an error value or NULL before putting the pinctrl device and verifying that the pinctrl device is present in 'pinctrldev_list' before removing. Fixes: df61b366af26 ('pinctrl: core: Use delayed work for hogs') Signed-off-by: NJon Hunter <jonathanh@nvidia.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 03 1月, 2017 11 次提交
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由 Linus Walleij 提交于
3bfd4430 ("pinctrl: amd: Add support for additional GPIO") created the following warning: drivers/pinctrl/pinctrl-amd.c: In function 'amd_gpio_dbg_show': drivers/pinctrl/pinctrl-amd.c:210:3: warning: 'pin_num' may be used uninitialized in this function [-Wmaybe-uninitialized] for (; i < pin_num; i++) { ^ drivers/pinctrl/pinctrl-amd.c:172:21: warning: 'i' may be used uninitialized in this function [-Wmaybe-uninitialized] unsigned int bank, i, pin_num; ^ Fix this by adding a guarding default case for illegal bank numbers. Cc: S-k Shyam-sundar <Shyam-sundar.S-k@amd.com> Cc: Nehal Shah <Nehal-bakulchandra.Shah@amd.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Gary Bisson 提交于
Now using function_desc structure instead of imx_pmx_func. Also leveraging generic functions to retrieve functions count/name/groups. The imx_free_funcs function can be removed since it is now handled by the core driver during unregister. Signed-off-by: NGary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Gary Bisson 提交于
Now using group_desc structure instead of imx_pin_group. Also leveraging generic functions to retrieve groups count/name/pins. The imx_free_pingroups function can be removed since it is now handled by the core driver during unregister. Finally the device tree parsing is moved after the pinctrl driver registration since this latter initializes the radix trees. Signed-off-by: NGary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Linus Walleij 提交于
These four pins are for SDC4, not SDC1. They are grouped for SDC4 later in the file so this must be a typo. Reviewed-by: NBjörn Andersson <bjorn.andersson@linaro.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Tony Lindgren 提交于
We can now drop the driver specific code for managing functions. Signed-off-by: NTony Lindgren <tony@atomide.com> [Replaces GENERIC_PINMUX with GENERIC_PINMUX_FUNCTIONS] Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Tony Lindgren 提交于
We can now drop the driver specific code for managing groups. Signed-off-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Tony Lindgren 提交于
We can add generic helpers for function handling for cases where the pin controller driver does not need to use static arrays. Signed-off-by: NTony Lindgren <tony@atomide.com> [Renamed the Kconfig item and moved things around] Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Linus Walleij 提交于
Rename the symbol PINCTRL_GENERIC to PINCTRL_GENERIC_GROUPS since it all pertains to groups. Replace everywhere. ifdef out the radix tree and the struct when not using the generic groups. Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Tony Lindgren 提交于
We can add generic helpers for pin group handling for cases where the pin controller driver does not need to use static arrays. Signed-off-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Linus Walleij 提交于
It confused me a bit so it may confuse others. Make it crystal clear what is going on here for any future readers. Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Tony Lindgren 提交于
Having the pin control framework call pin controller functions before it's probe has finished is not nice as the pin controller device driver does not yet have struct pinctrl_dev handle. Let's fix this issue by adding deferred work for late init. This is needed to be able to add pinctrl generic helper functions that expect to know struct pinctrl_dev handle. Note that we now need to call create_pinctrl() directly as we don't want to add the pin controller to the list of controllers until the hogs are claimed. We also need to pass the pinctrl_dev to the device tree parser functions as they otherwise won't find the right controller at this point. Signed-off-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 30 12月, 2016 9 次提交
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由 Gary Bisson 提交于
This change is inspired from the pinctrl-single architecture. The problem with current implementation is that it isn't possible to add/remove functions and/or groups dynamically. The radix tree offers an easy way to do so. The intent is to offer a follow-up patch later that will enable the use of pinctrl nodes in dt-overlays. Signed-off-by: NGary Bisson <gary.bisson@boundarydevices.com> Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Gary Bisson 提交于
Otherwise can't dynamically update fields such as ngroups which can change over time (with a dt-overlay for instance). Signed-off-by: NGary Bisson <gary.bisson@boundarydevices.com> Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Colin Ian King 提交于
Trivial fixe to spelling mistake "Ivalid" to "Invalid" in dev_err error message. Signed-off-by: NColin Ian King <colin.king@canonical.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Vladimir Zapolskiy 提交于
This is a non-functional change, which deletes code duplication in two of four if-if branches by reordering the checks. Functional identity of the code change can be shown by running through the whole truth table of boolean arguments. Signed-off-by: NVladimir Zapolskiy <vz@mleia.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 John Crispin 提交于
This patch updates my email address as I no longer have access to the old one. Signed-off-by: NJohn Crispin <john@phrozen.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Christophe JAILLET 提交于
Add some tab in order to improve indentation. Signed-off-by: NChristophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Christophe JAILLET 提交于
Reference to 'sys2pci_np' should be dropped in all cases here, not only in error handling path. Signed-off-by: NChristophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Gabriel Fernandez 提交于
This activates strict mode muxing for the STM32 pin controllers, as these do not allow GPIO and functions to use the same pin simultaneously. Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com> Acked-by: NPatrice Chotard <patrice.chotard@st.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Andreas Klinger 提交于
On Marvell mv88f6180 mpp pins range from 0 to 19 as well as from 35 to 44. This is already fixed in commit: 9573e792 This is the documentation change for above commit. Signed-off-by: NAndreas Klinger <ak@it-klinger.de> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 28 12月, 2016 6 次提交
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由 Shah, Nehal-bakulchandra 提交于
This patch adds support for new Bank and adds IRQCHIP_SKIP_SET_WAKE flag. Reviewed-by: NS-k, Shyam-sundar <Shyam-sundar.S-k@amd.com> Signed-off-by: NNehal Shah <Nehal-bakulchandra.Shah@amd.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Andrew Jeffery 提交于
Signed-off-by: NAndrew Jeffery <andrew@aj.id.au> Acked-by: NJoel Stanley <joel@jms.id.au> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Andrew Jeffery 提交于
The patch introducing the g5 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms and the AST2500 evaluation board. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Signed-off-by: NAndrew Jeffery <andrew@aj.id.au> Acked-by: NJoel Stanley <joel@jms.id.au> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Andrew Jeffery 提交于
The patch introducing the g4 pinctrl driver implemented a smattering of pins to flesh out the implementation of the core and provide bare-bones support for some OpenPOWER platforms. Now, update the bindings document to reflect the complete functionality and implement the necessary pin configuration tables in the driver. Cc: Timothy Pearson <tpearson@raptorengineering.com> Signed-off-by: NAndrew Jeffery <andrew@aj.id.au> Acked-by: NJoel Stanley <joel@jms.id.au> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Andrew Jeffery 提交于
The System Control Unit IP block in the Aspeed SoCs is typically where the pinmux configuration is found, but not always. A number of pins depend on state in one of LPC Host Control (LHC) or SoC Display Controller (GFX) IP blocks, so the Aspeed pinmux drivers should have the means to adjust these as necessary. We use syscon to cast a regmap over the GFX and LPC blocks, which is used as an arbitration layer between the relevant driver and the pinctrl subsystem. The regmaps are then exposed to the SoC-specific pinctrl drivers by phandles in the devicetree, and are selected during a mux request by querying a new 'ip' member in struct aspeed_sig_desc. Signed-off-by: NAndrew Jeffery <andrew@aj.id.au> Reviewed-by: NJoel Stanley <joel@jms.id.au> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Andrew Jeffery 提交于
Reference the SoC-specific compatible string in the examples as required. Signed-off-by: NAndrew Jeffery <andrew@aj.id.au> Acked-by: NJoel Stanley <joel@jms.id.au> Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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- 26 12月, 2016 1 次提交
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由 Linus Torvalds 提交于
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