Legacy and old PCI I/O based cards do not support 32-bit I/O addressing.

Since commit 64f160e1 ("PCI: aardvark: Configure PCIe resources from
'ranges' DT property") kernel can set different PCIe address on CPU and
different on the bus for the one A37xx address mapping without any firmware
support in case the bus address does not conflict with other A37xx mapping.

So remap I/O space to the bus address 0x0 to enable support for old legacy
I/O port based cards which have hardcoded I/O ports in low address space.

Note that DDR on A37xx is mapped to bus address 0x0. And mapping of I/O
space can be set to address 0x0 too because MEM space and I/O space are
separate and so do not conflict.

Remapping IO space on Turris Mox to different address is not possible to
due bootloader bug.
Signed-off-by: NPali Rohár <pali@kernel.org>
Reported-by: NArnd Bergmann <arnd@arndb.de>
Fixes: 76f6386b ("arm64: dts: marvell: Add Aardvark PCIe support for Armada 3700")
Cc: stable@vger.kernel.org # 64f160e1 ("PCI: aardvark: Configure PCIe resources from 'ranges' DT property")
Cc: stable@vger.kernel.org # 514ef1e6 ("arm64: dts: marvell: armada-37xx: Extend PCIe MEM space")
Reviewed-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

Kernel driver phy-mvebu-a3700-comphy.c needs to know the rate of the
reference xtal clock. So add missing xtal clock source into comphy device
tree node. If the property is not present, the driver defaults to 25 MHz
xtal rate (which, as far as we know, is used by all the existing boards).
Signed-off-by: NPali Rohár <pali@kernel.org>
Signed-off-by: NMarek Behún <kabel@kernel.org>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

Current PCIe MEM space of size 16 MB is not enough for some combination
of PCIe cards (e.g. NVMe disk together with ath11k wifi card). ARM Trusted
Firmware for Armada 3700 platform already assigns 128 MB for PCIe window,
so extend PCIe MEM space to the end of 128 MB PCIe window which allows to
allocate more PCIe BARs for more PCIe cards.

Without this change some combination of PCIe cards cannot be used and
kernel show error messages in dmesg during initialization:

    pci 0000:00:00.0: BAR 8: no space for [mem size 0x01800000]
    pci 0000:00:00.0: BAR 8: failed to assign [mem size 0x01800000]
    pci 0000:00:00.0: BAR 6: assigned [mem 0xe8000000-0xe80007ff pref]
    pci 0000:01:00.0: BAR 8: no space for [mem size 0x01800000]
    pci 0000:01:00.0: BAR 8: failed to assign [mem size 0x01800000]
    pci 0000:02:03.0: BAR 8: no space for [mem size 0x01000000]
    pci 0000:02:03.0: BAR 8: failed to assign [mem size 0x01000000]
    pci 0000:02:07.0: BAR 8: no space for [mem size 0x00100000]
    pci 0000:02:07.0: BAR 8: failed to assign [mem size 0x00100000]
    pci 0000:03:00.0: BAR 0: no space for [mem size 0x01000000 64bit]
    pci 0000:03:00.0: BAR 0: failed to assign [mem size 0x01000000 64bit]

Due to bugs in U-Boot port for Turris Mox, the second range in Turris Mox
kernel DTS file for PCIe must start at 16 MB offset. Otherwise U-Boot
crashes during loading of kernel DTB file. This bug is present only in
U-Boot code for Turris Mox and therefore other Armada 3700 devices are not
affected by this bug. Bug is fixed in U-Boot version 2021.07.

To not break booting new kernels on existing versions of U-Boot on Turris
Mox, use first 16 MB range for IO and second range with rest of PCIe window
for MEM.
Signed-off-by: NPali Rohár <pali@kernel.org>
Fixes: 76f6386b ("arm64: dts: marvell: Add Aardvark PCIe support for Armada 3700")
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

UART1 (standard variant with DT node name 'uart0') has register space
0x12000-0x12018 and not whole size 0x200. So fix also this in example.
Signed-off-by: NPali Rohár <pali@kernel.org>
Fixes: c737abc1 ("arm64: dts: marvell: Fix A37xx UART0 register size")
Link: https://lore.kernel.org/r/20210624224909.6350-6-pali@kernel.orgSigned-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Move the turris-mox-rwtm firmware node from Turris MOX' device tree into
the generic armada-37xx.dtsi file and use the generic compatible string
'marvell,armada-3700-rwtm-firmware' instead of the current one.

Turris MOX DTS file contains also old compatible string for backward
compatibility.

The Turris MOX rWTM firmware can be used on any Armada 37xx device,
giving them access to the rWTM hardware random number generator, which
is otherwise unavailable.

This change allows Linux to load the turris-mox-rwtm.ko module on these
boards.

Tested on ESPRESSObin v5 with both default Marvell WTMI firmware and
CZ.NIC's firmware. With default WTMI firmware the turris-mox-rwtm fails
to probe, while with CZ.NIC's firmware it registers the HW random number
generator.
Signed-off-by: NPali Rohár <pali@kernel.org>
Signed-off-by: NMarek Behún <kabel@kernel.org>
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

Add "syscon" compatible to the North Bridge clocks node to allow the
cpufreq driver to access these registers via syscon API.

This is needed for a fix of cpufreq driver.
Signed-off-by: NMarek Behún <kabel@kernel.org>
Fixes: e8d66e79 ("arm64: dts: marvell: armada-37xx: add nodes...")
Cc: stable@vger.kernel.org
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

SATA on A3720 SOC can use only comphy2, so move this definition from board
specific DTS file armada-3720-espressobin.dtsi into main A3720 SOC file
armada-37xx.dtsi.
Signed-off-by: NPali Rohár <pali@kernel.org>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

Group name 'pcie1' is misleading as it controls only PCIe reset pin. Like
other PCIe groups it should have been called 'pcie1_reset'. But due to
backward compatibility it is not possible to change existing group name.
So just add comment describing this PCIe reset functionality.
Signed-off-by: NPali Rohár <pali@kernel.org>
Link: https://lore.kernel.org/r/20200724132457.7094-1-pali@kernel.orgSigned-off-by: NLinus Walleij <linus.walleij@linaro.org>

Move the max-link-speed property of the PCIe node from board specific
device tree files to the generic armada-37xx.dtsi.

Armada 37xx supports only PCIe gen2 speed so max-link-speed property
should be in the generic armada-37xx.dtsi file.
Signed-off-by: NPali Rohár <pali@kernel.org>
Tested-by: NTomasz Maciej Nowak <tmn505@gmail.com>
Acked-by: NThomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

Move the comphy handle property of the PCIe node from board specific
device tree files (EspressoBin and Turris Mox) to the generic
armada-37xx.dtsi.

This is correct since this is the only possible PCIe PHY configuration
on Armada 37xx, so when PCIe is enabled on any board, this handle is
correct.
Signed-off-by: NMarek Behún <marek.behun@nic.cz>
Tested-by: NTomasz Maciej Nowak <tmn505@gmail.com>
Acked-by: NThomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

We found out that we are unable to control the PERST# signal via the
default pin dedicated to be PERST# pin (GPIO2[3] pin) on A3700 SOC when
this pin is in EP_PCIE1_Resetn mode. There is a register in the PCIe
register space called PERSTN_GPIO_EN (D0088004[3]), but changing the
value of this register does not change the pin output when measuring
with voltmeter.

We do not know if this is a bug in the SOC, or if it works only when
PCIe controller is in a certain state.

Commit f4c7d053 ("PCI: aardvark: Wait for endpoint to be ready
before training link") says that when this pin changes pinctrl mode
from EP_PCIE1_Resetn to GPIO, the PERST# signal is asserted for a brief
moment.

So currently the situation is that on A3700 boards the PERST# signal is
asserted in U-Boot (because the code in U-Boot issues reset via this pin
via GPIO mode), and then in Linux by the obscure and undocumented
mechanism described by the above mentioned commit.

We want to issue PERST# signal in a known way, therefore this patch
changes the pcie_reset_pin function from "pcie" to "gpio" and adds the
reset-gpios property to the PCIe node in device tree files of
EspressoBin and Armada 3720 Dev Board (Turris Mox device tree already
has this property and uDPU does not have a PCIe port).
Signed-off-by: NMarek Behún <marek.behun@nic.cz>
Cc: Remi Pommarel <repk@triplefau.lt>
Tested-by: NTomasz Maciej Nowak <tmn505@gmail.com>
Acked-by: NThomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

This adds pinctrl node for the GPIO to be used as SPI chip select 1.
Signed-off-by: NMarek Behún <marek.behun@nic.cz>
Cc: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

This adds the rWTM BIU mailbox node for communication with the secure
processor. The driver already exists in
drivers/mailbox/armada-37xx-rwtm-mailbox.c.
Signed-off-by: NMarek Behún <marek.behun@nic.cz>
Cc: Gregory Clement <gregory.clement@bootlin.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

Reference the PHY nodes from the USB controller nodes.

The USB3 host controller is wired to:
  * the first PHY of the COMPHY IP
  * the OTG-capable UTMI PHY

The USB2 host controller is wired to:
  * the host-only UTMI PHY
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

Describe the A3700 COMPHY node. It has three PHYs that can be
configured as follow:
* PCIe or GbE
* USB3 or GbE
* SATA or USB3
Each of them has its own memory area.
Suggested-by: NGrzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

In order to be able to communicate with the 88e6341 switch some pins
have to be repurposed as RGMII and SMI pins.

This fixes ethernet support on system booted via a bootloader that
has not already configured those pins (e.g. mainline u-boot, or vendor
u-boot compiled without ethernet support).
Signed-off-by: NRemi Pommarel <repk@triplefau.lt>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

One pin can be muxed as PCIe endpoint card reset.
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

On Marvell Armada 3700 SoCs there are two USB2 UTMI PHYs. They are
both very similar but only one has OTG/charging capabilities.

Because there are USB host registers and PHY registers mixed in a
single area, a system controller is also created and referenced from
both the USB host node and the PHY node.
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

The specification splits the USB2 memory region into three sections:
1/ 0xD005E000-0xD005EFFF: USB2 Host Controller Registers
2/ 0xD005F000-0xD005F7FF: USB2 UTMI PHY Registers
3/ 0xD005F800-0xD005FFFF: USB2 Host Miscellaneous Registers

Section 1/ belongs to the USB2 node but section 2/ belongs to the UTMI
PHY node. Section 3/ can be accessed by both the USB controller and
the PHY because of the miscaellaneous nature of the registers inside
so a specific node will be created to cover the area and a handle to
it will be added in both the USB controller and the PHY node.
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

The SATA IP get its clock from the north-bridge.
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

Fix the SATA IP memory area which is only 0x178 bytes long (from
Marvell A3700 specification). Actually, starting from the offset
0xe0178, there is an area dedicated to the COMPHY driver.
Suggested-by: NGrzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

The 'arm,armv8' compatible string is only for software models. It adds
little value otherwise and is inconsistently used as a fallback on some
platforms. Remove it from those platforms.

This fixes warnings generated by the DT schema.
Reported-by: NMichal Simek <michal.simek@xilinx.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Acked-by: NAntoine Tenart <antoine.tenart@bootlin.com>
Acked-by: NNishanth Menon <nm@ti.com>
Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>
Acked-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: NChanho Min <chanho.min@lge.com>
Acked-by: NKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: NGregory CLEMENT <gregory.clement@bootlin.com>
Acked-by: NThierry Reding <treding@nvidia.com>
Acked-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NSimon Horman <horms+renesas@verge.net.au>
Acked-by: NTero Kristo <t-kristo@ti.com>
Acked-by: NWei Xu <xuwei5@hisilicon.com>
Acked-by: NLiviu Dudau <liviu.dudau@arm.com>
Acked-by: NMatthias Brugger <matthias.bgg@gmail.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NScott Branden <scott.branden@broadcom.com>
Acked-by: NKevin Hilman <khilman@baylibre.com>
Acked-by: NChunyan Zhang <zhang.lyra@gmail.com>
Acked-by: NRobert Richter <rrichter@cavium.com>
Acked-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com>
Acked-by: NDinh Nguyen <dinguyen@kernel.org>
Signed-off-by: NRob Herring <robh@kernel.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add emmc/sdio pinctrl definition for marvell armada37xx SoCs.
Signed-off-by: NDing Tao <miyatsu@qq.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

Aligned with what we have done for the others nodes. It will also allow
to easily modify the cpu configuration at board (or sub-SoC) level.
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

This adds the system controller node for CPU Miscellaneous Registers
(which is needed for the watchdog node) and the watchdog node.
Signed-off-by: NMarek Behún <marek.behun@nic.cz>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

New compatibles are now supported by the Inside Secure SafeXcel driver.
As they are more specific than the old ones, they should be used
whenever possible. This patch updates the Marvell Armada 37xx device
tree accordingly.
Signed-off-by: NAntoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

The PSCI area should be reserved in Linux for PSCI operations such as
suspend/resume.

Reserve 2MiB of memory which matches the area used by ATF (BL1, BL2,
BL3x, see [1] in ATF source code). This covers all PSCI code and data
area and is 2MiB aligned, which is required by Linux for huge pages
handling.

Please note that this is a default setup allowing to perform PSCI
operations with legacy bootloaders. Recent bootloaders should update the
region size/position accordingly.

[1] plat/marvell/a3700/common/include/platform_def.h
Signed-off-by: NVictor Gu <xigu@marvell.com>
[miquel.raynal@bootlin.com: reword of commit message, comment in the DTSI]
Signed-off-by: NMiquel Raynal <miquel.raynal@bootlin.com>
Acked-by: NThomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

In order to be able to use Adaptive Voltage Scaling, we need to add a
reference to these registers.
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

This allows to reference these gpio controller as interrupt parent. Also
add a comment which cpu line names are managed by the controllers
because "nb" and "sb" usually doesn't appear in schematics, but MPPX_Y
do.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

Follow the recent trend for the license description, and also fix the
wrongly stated X11 to MIT.

As already pointed on the DT ML, the X11 license text [1] is explicitly
for the X Consortium and has a couple of extra clauses. The MIT
license text [2] is actually what the current DT files claim.

[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.htmlSigned-off-by: NGregory CLEMENT <gregory.clement@bootlin.com>

This patch adds a crypto node describing the EIP97 engine found in
Armada 37xx SoCs. The cryptographic engine is enabled by default.
Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

In order to be able to use cpu freq, we need to associate a clock to each
CPU and to expose the power management registers.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

Add a node in Armada 37xx DTSI file for the second UART, with a
different compatible due to its extended IP which has some
differences with the first UART already in place.

Make use of this commit to also fully describe the first port and
use the same clear and named interrupt bindings for both ports.

The standard UART (UART0) uses level-interrupts while the extended
UART (UART1) uses edge-triggered interrupts.
Signed-off-by: NMiquel Raynal <miquel.raynal@free-electrons.com>
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

Add the missing clock property to armada-3700 UART node.

This clock will be used to derive the prescaler value to comply with
the requested baudrate.
Signed-off-by: NMiquel Raynal <miquel.raynal@free-electrons.com>
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

Cosmetic patch removing an empty line at the end of the NB pinctrl node.
Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

Armada-37xx UART0 registers are 0x200 bytes wide. Right next to them are
the UART1 registers that should not be declared in this node.

Update the example in DT bindings document accordingly.
Signed-off-by: Nallen yan <yanwei@marvell.com>
Signed-off-by: NMiquel Raynal <miquel.raynal@free-electrons.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

The Cortex-A53s that power the Armada-37xx SoCs are equipped with
a PMUv3, just like most ARMv8 cores.

Advertise the PMUv3 presence in the device tree, and wire its
interrupt. This allows the perf subsystem to work correctly.
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

The Cortex-A53s that power the Armada-37xx SoCs are equipped with
a GIC CPU interface that gets enabled when coupled with a GICv3
interrupt controller, such as the GIC-500 on the this SoC.

Advertise the MMIO ranges provided by the CPUs, which enables
(among other things) GICv2 guests to run under a hypervisor such
as KVM.
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

The GIC-500 integrated in the Armada-37xx SoCs is compliant with
the GICv3 architecture, and thus provides a maintenance interrupt
that is required for hypervisors to function correctly.

With the interrupt provided in the DT, KVM now works as it should.
Tested on an Espressobin system.

Fixes: adbc3695 ("arm64: dts: add the Marvell Armada 3700 family and
a development board")
Cc: <stable@vger.kernel.org>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>

The number of pins in South Bridge is 30 and not 29. There is a fix for
the driver for the pinctrl, but a fix is also need at device tree level
for the GPIO.

Fixes: afda007f ("ARM64: dts: marvell: Add pinctrl nodes for Armada
3700")
Cc: <stable@vger.kernel.org>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>