- 23 4月, 2013 1 次提交
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由 Daniel Lezcano 提交于
The en_core_tk_irqen flag is set in all the cpuidle driver which means it is not necessary to specify this flag. Remove the flag and the code related to it. Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Kevin Hilman <khilman@linaro.org> # for mach-omap2/* Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
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- 09 4月, 2013 2 次提交
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由 Daniel Lezcano 提交于
dev->state_count is initialized automatically by cpuidle_register_device(). When drv->state_count is equal to dev->state_count, no need to init this field, so removing it. Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: NJoseph Lo <josephl@nvidia.com> Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
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由 Daniel Lezcano 提交于
Initialize the idle states directly in the driver structure. That prevents extra structure declaration and memcpy at init time. Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: NJoseph Lo <josephl@nvidia.com> Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
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- 29 1月, 2013 2 次提交
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由 Joseph Lo 提交于
The "powered-down" cpuidle mode of Tegra20 needs the CPU0 be the last one core to go into this mode before other core. The coupled cpuidle framework can help to sync the MPCore to coupled state then go into "powered-down" idle mode together. The driver can just assume the MPCore come into "powered-down" mode at the same time. No need to take care if the CPU_0 goes into this mode along and only can put it into safe idle mode (WFI). The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI for waiting CPU0 in the same state. When the CPU0 requests powered-down state, it attempts to put the secondary CPU into reset to prevent it from waking up. Then power down both CPUs together and power off the cpu rail. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by: NJoseph Lo <josephl@nvidia.com> Acked-by: NColin Cross <ccross@android.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Joseph Lo 提交于
The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI. The Tegra20 had a limition to power down both CPU cores. The secondary CPU must waits for CPU0 in powered-down state too. If the secondary CPU be woken up before CPU0 entering powered-down state, then it needs to restore its CPU states and waits for next chance. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by: NJoseph Lo <josephl@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 16 11月, 2012 2 次提交
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由 Joseph Lo 提交于
The different Tegra chips may have different CPU idle states and data. Individual CPU idle driver make it more easy to maintain. Signed-off-by: NJoseph Lo <josephl@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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由 Joseph Lo 提交于
The Tegra CPU idle LP3 state is doing ARM WFI only. So it's same with the common ARM_CPUIDLE_WFI_STATE. Using it to replace LP3 now. Signed-off-by: NJoseph Lo <josephl@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 06 11月, 2012 1 次提交
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由 Stephen Warren 提交于
This should make it easier to delete or move <mach/*.h>; something that is useful for single-zImage. Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 12 6月, 2012 1 次提交
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由 Prashant Gaikwad 提交于
This particular code had no effect on WFI execution. It only asserts/de-asserts signal to tegra "legacy" CPU idle stats monitor, which we are no longer using (cpufreq is based on kernel s/w idle stats instead). Signed-off-by: NPrashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: NStephen Warren <swarren@nvidia.com>
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- 07 2月, 2012 1 次提交
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由 Peter De Schrijver 提交于
CPUidle driver for tegra. In this version only LP3 (clockgating) is supported. Based on work by: Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com> Acked-by: NStephen Warren <swarren@nvidia.com> Tested-by: NStephen Warren <swarren@nvidia.com> Acked-by: NColin Cross <ccross@android.com> Signed-off-by: NOlof Johansson <olof@lixom.net>
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